812FAQs.pdf

ADuC812 FAQs

M ICRO C ONVERTER G ENERIC

L AYOUT AND D ESIGN C ONSIDERATIONS

Q: The MicroConverter has separate pins for analog and digital grounds . Should I connect these to

two separate ground planes on my board?

A: No. At least, not unless the two ground planes are connected together very near the chip. In all

other situations, it is best to keep the MicroConverter on a single ground plane. If you have two

separate ground planes on your board, then place the MicroConverter on the quieter of the two

(usually the analog plane) to obtain optimum ADC and DAC performance.

Q: I have some fast logic edges on some of the digital circuitry I plan to connect to the

MicroConverter. Will these signals impact the analog performance of the chip?

A: Signals with rise and fall times of less than 5ns or so, when applied directly to a MicroConverter’s

digital input pins, can potentially feed through and degrade analog performance. A simple solution

to this problem is found in the form of a series resistor. A series resistor of around 200W will slow

an edge sufficiently that it won’t affect the MicroConverter’s analog performance.

M ISCELLANEOUS

Q: When a MicroConverter DAC is disabled, what does it’s output look like? Is there a DAC “tri-

state” feature?

A: MicroConverter DACs default to a disabled state when the chip is powered up. In this state, the

output appears as a high impedance node to the rest of the world. This is analogous to a “tri-state”

type output in digital logic terms. You can place the DAC output into this high impedance state

whenever you like simply by disabling the DAC again.

Q: I heard that the MicroConverter can address up to 16Mbytes of external data memory . Is this

true and how is it done?

A: Yes, the MicroConverter can address up to 16Mbytes of external data memory. If access to more

than 64 Kbytes of RAM is desired, a feature unique to the MicroConverter allows addressing up to

16 Mbytes of external RAM simply by adding an additional latch on the Port 2 address bus.

On a standard 8051 as with the MicroConverter Port 0 (P0) serves as a multiplexed address/data

bus. It emits the low byte of the data pointer (DPL) as an address, which is latched by a pulse of

ALE prior to data being placed on the bus by the MicroConverter (write operation) or the SRAM

(read operation). Port 2 (P2) provides the data pointer page byte (DPP) to be latched by ALE,

followed by the data pointer high byte (DPH). If no latch is connected to P2, DPP is ignored by the

SRAM, and the 8051 standard of 64kByte external data memory access is maintained.

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ADuC812 FAQs

Q: I would like to serially download new code to the MicroConverter using my host machine. What is

the serial download protocol used to reprogram the MicroConverter?

A: MicroConverters can be serially reprogrammed in your system using Analog Devices’ Windows

based download program (WSD.exe) to communicate through the chip’s UART. Alternatively,

you can in-system-reprogram the MicroConverter from any other host processor using the same

serial download protocol used by the WSD application. Refer to tech note uC004 available on the

web or as part of the QuickStart Development System.

Q: What’s this “ power-on configuration routine ” that I’ve heard about?

A: Every MicroConverter product features a “power-on configuration routine” that runs every time

you apply power to the chip or reset it. Basically, this is a small piece of code that is executed prior

to the execution of your code. It is used to configure some of the on-chip peripherals such as the

ADC and Flash/EE memory with factory optimized calibration and timing parameters. Some of

these you can see (for example, default ADC offset and gain calibration registers will be different

from one chip to the next) and others you can’t (for example, ADC linearity, PTAT coefficients are

not visible to your code). For the MicroConverter devices that run off a 32kHz crystal the power

on configuration will also wait for the part to ‘lock’ before it starts to run user code.

The power-on configuration routine is stored in a hidden area of program ROM. The address

where the routine begins is FF00 hex. Although the power-on configuration routine is “mapped” to

addresses FF00 through FFFF hex, this does not interfere with external code memory which shares

these addresses. Up to 64K bytes of user code can be executed from an external PROM chip (or

8K from internal Flash/EE and 56K from external PROM).

The ALE output is automatically disabled during the execution of the power-on configuration

routine so that you can tell when your code starts to execute. ALE only begins toggling when the

first line of your code is executed.

Q: The PSEN pin is always an output on an 8051. How then can it be used as an input to enter serial

download mode? What pulldown resistor should be used to be sure to enter serial download

mode? Is the standard functionality of the PSEN pin affected?

A: On an 8051 the PSEN pin is always an output. It is used to access from external code memory. On

the MicroConverter the PSEN pin is used to access external code memory and is used as an input

to determine whether to run user code or run the on chip serial downloader.

The PSEN pin is normally configured as an output. When the RESET pin is pulled high, the

PSEN pin becomes a digital input and the voltage at the PSEN pin is sampled every machine

cycle. Once the RESET pin is released (low) the last sampled logic level of the PSEN pin is used

to decide whether to run from user code or whether to run the on chip serial downloader.

To ensure that the PSEN pin is interpreted as a logic low it should be pulled low through a 1k

resistor to ground. To ensure that the PSEN pin is interpreted as a logic high it can be left float as

there is an internal pullup resistor.

Because the functionality of the PSEN pin on the MicroConverter only differs from that of an

8051 when RESET is pulled high (in this condition the PSEN pin on an 8051 is useless) the

functionality of the PSEN pin on the MicroConverter is unaffected by its additional functionality.

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ADuC812 FAQs

Q: Do I have to enter “NOP” instructions to wait for the Flash/EE erase and program times to

elapse before performing the next data Flash/EE operation?

A: Absolutely not. All timing for access to the data Flash/EE space is taken care of for you in

hardware. When you perform a Flash/EE erase or program command, the MCU core will not

move on to the next machine cycle until the Flash/EE operation is complete. Effectively this means

that a Flash/EE erase or program command will only take one machine cycle, but that this machine

cycle is stretched out over a 20ms/250µs period for a Flash/EE erase/program command on the

ADuC812 or over a 2ms/250µs period for a Flash/EE erase/program command for the ADuC824.

Q: What happens if the power supply falls during a program or erase of the Flash/EE data

memory?

A: If the power supply falls below 2.7V during a Flash/EE program or erase instruction then the core

cannot guarantee that the instruction will execute correctly.

Also, because the Flash/EE program or erase instruction takes much longer than a typical

instruction (250us for a program and 2ms/20ms (ADuC824/ADuC812) for an erase), the time

required to respond to interrupts can be greatly increased if the interrupt occurs during a flash/EE

program or erase instruction.

For instance, if a power-supply-monitor (PSM) interrupt occurs during a Flash/EE program or

erase instruction, it will only be processed after the instruction is complete. In this way, the PSM

can be used to indicate when power has dropped below a specified threshold during a Flash/EE

program or erase instruction, thereby indicating that the instruction may not have executed

correctly.

Q: Are there any sockets available for the52PQFP package ?

A: Yes, but only test or evaluation type sockets. They aren't suitable for production since they are ZIF

types that cost many times the price of the MicroConverter products. They can, however, prove

useful for test/programming heads or in some cases for debug/prototyping setups. A couple of

different types include the below....

Enplas:

OTQ-52-0.65-01: "open-top" type

FPQ-52-0.65-01A: "clam-shell" type

(sockets mount on through-hole pattern, useful for test/programming heads.)

Ironwood Electronics:

CA-QFE52SB-L-Z-T-01: socket module

SF-QFE52SB-L-01: board header

(board header solders to 52PQFP footprint, and socket adapter plugs into it to accept

MicroConverter package. also provides test point connections to all 52 pins. useful for

debug/prototyping setups.)

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ADuC812 FAQs

AD U C812 S PECIFIC

AD U C812 ADC:

Q: Can I connect a high impedance analog source directly to one of the ADuC812’s inputs? Or

must I buffer the signal first?

A: The main limitation with high impedance sources is the input leakage current of the ADuC812’s

analog inputs, which is typically ±1µA. This current flowing through a source impedance of 610W

will generate 610µV of error. With a 2.5V reference, this is 1LSB (or 2.5V/4096). Therefore, a

source impedance of greater than 610W can potentially generate measurable DC errors.

Q: Some feature lists talk about the “ self calibration ” capabilities of the ADuC812. How do I make

use of this feature? Will this calibrate the ADuC812’s ADC offset and gain errors ?

A: “Self calibration” of the ADuC812 involves the use of a software routine described in the tech note

uC005. Refer to application note uC005, available on the web at

www.analog.com/microconverter/technotes_code.html . This calibration procedure will calibrate

the ADuC812’s ADC for offset and gain errors.

Q: What acquisition time is required by the ADuC812? How do I choose the proper values for the

acquisition time select bits in ADCCON1?

A: In nearly all cases, an acquisition time of 1 ADC clock (ADCCON1.2=0, ADCCON1.3=0) will

provide plenty of time for the ADuC812 to acquire its signal before switching the internal

track&hold amplifier in to hold mode. The only exception would be a high source impedance

analog input, but these should be buffered first anyway since source impedances of greater than

610W can cause DC errors as well.

Q: How do I choose the conversion time in the ADuC812’s ADCCON1 register? And what are these

ADC clock divide bits anyway?

A: The ADuC812’s successive approximation ADC is driven by a divided down version of the master

clock. To ensure adequate ADC operation, this ADC clock must be between 400KHz and 4MHz.,

and optimum performance is obtained with ADC clock between 400KHz and 3MHz. Frequencies

within this range can easily be achieved with master clock frequencies from 400KHz to well above

16MHz with the four ADC clock divide ratios to choose from. For example, with a 12MHz master

clock, set the ADC clock divide ratio to 4 (i.e. ADC CLK = M CLK / 4 = 3MHz) by setting the

appropriate bits in ADCCON1 (ADCCON1.5=1, ADCCON1.4=0).

The total ADC conversion time is 15 ADC clocks, plus 1 ADC clock for synchronization, plus the

selected acquisition time (1, 2, 3, or 4 ADC clocks). For the example above, with a 1 clock

acquisition time, total conversion time is 17 ADC clocks (or 5.67µs for a 3MHz ADC clock).

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ADuC812 FAQs

Q: How do I determine the ADuC812’s sample rate in continuous conversion mode ?

A: In continuous conversion mode, a new conversion begins each time the previous one finishes. The

sample rate is then simply the inverse of the total conversion time described above. In the example

above, the continuous conversion mode sample rate would be 176.5KHz.

Q: What is the ADuC812’s aperture delay in hardware CONVST mode? And what aperture

uncertainty can I expect?

A: In hardware CONVST mode an external logic input is used to trigger ADC conversions. The

aperture delay of the ADuC812 is the time from the rising edge of that external trigger to the

moment when the sample & hold amplifier goes into hold mode. This time is equal to the

acquisition time (selected via ADCCON1) plus a synchronization time of between 0.5 and 1.5

ADC clock periods.

When the CONVST trigger is asynchronous to the ADC clock, this results in an aperture

uncertainty of 1 ADC clock period. This aperture uncertainty can be avoided by synchronizing the

external CONVST signal with the ADC clock. Since the ADC clock is simply a divided down

master clock it is not available to you directly. Therefore, to synchronize your CONVST signal

with the ADC clock, you must synchronize it with a divided master clock, where the divide ratio is

a direct multiple of the divide ratio used to generate the ADC clock (selected in ADCCON1).

Q: What happens if the ADuC812 receives a second CONVST trigger (software SCONV, Timer2

trigger, or hardware CONVST trigger) during a conversion that it hasn’t yet completed?

A: The second CONVST trigger will be ignored. In this situation, the second trigger event is lost. To

avoid this loss of samples, make sure your software checks the state of the ADC busy flag

(ADCCON3.7) before starting a conversion. In timer driven or hardware driven conversion

modes, make sure the timer overflow rate or the input edge rate is more that the ADC conversion

time plus acquisition time (controlled by ADCCON1).

AD U C812 V OLTAGE R EFERENCE :

Q: I’m using the ADuC812’s internal voltage reference . What should I do with the V REF and C REF

pins?

A: Decouple both to ground using 0.1µF chip capacitors with short trace lengths.

Q: I would like to drive other circuitry with the internal voltage reference of the ADuC812.

Should I take this voltage from the V REF pin or the C REF pin? What are the current source/sink

capabilities of these pins?

A: Use the V REF pin. The C REF pin is an internal node within the buffer. It’s voltage won’t be equal

to V REF . With regard to the ability of the V REF pin to sink and source current, it really has none. It

is effectively 2.5V with a nominally 50KW source impedance. You must buffer the voltage on this

pin if you wish to use the voltage to drive other circuitry. Of course, decouple the V REF and C REF

pins with 0.1µF chip capacitors to ground just as you would normally.

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