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SMALL CIRCUITS
COLLECTION
042
LF DAC Driver
A. Grace
Maxim, with various suffixes. It may be obtained from RS
Electronics at a price of about £8. Note that the AD7224 is
not equivalent with the ICM7224, which is a display driver!
The double-buffered interface logic of the DAC consists of
two 8-bit registers — an input register and a DAC register.
Both registers
are
made trans
parent by grounding the three
control
lines (CS, WR, LDAC). Under these conditions, the
RESET line functions as a zero override. This is achieved
at power up via the transistor buffered RC circuit of T2, R4
and C4.
The voltage output signal of the DAC is incremented under
the control of the outputs of a 12-bit counter type 4040
whose outputs are incremented in a binary fashion on the
falling edge of the clock pulse applied to pin 10 via K1.
Nine of the counter’s twelve outputs are used in this
design. Q0 to Q7 provide the 8 bit data for the DAC, and Q8
is used to control the slope of the DAC output signal via
XOR gates in IC2 and IC3. With output Q8 at logic 0 (count
less than 256), the outputs of IC2 and IC3 will have the
same output polarity as the output of the counter and the
output voltage of the DAC will increment. When the counter
reaches 256, Q8 will go high, and the outputs of the counter
will be inverted via XOR gates. This gives the effect of the
output voltage of the DAC decrementing, whilst the counter
continues to increment. The counter is also reset at power
up via a second reset circuit comprising of T1, R1 and C2.
The counter has the longer time constant to allow the DAC
This simple circuit was developed as a low-frequency (LF)
signal generator to exercise a temperature control system
used to control a process that can have a very large time
constant (i.e., the time taken for the output to reach equi-
librium after a change of input signal) of tens of minutes to
several hours. The circuit can be used to test a control sys-
tem out on the bench before being re-installed back in the
plant, or used as part of a demonstration rig.
The test circuit outputs a triangular voltage signal on K2
that ramps from zero to +5 V and then back down again to
0V. The time taken for one cycle is dependent upon the
clock signal fed into the circuit at K1. The circuit contains
an 8-bit DAC whose output will cycle from zero to maxi-
mum in 256 steps. With a 1 Hz clock signal at K1, the period
of the signal will take 2 times 256 seconds or approx. 8.5
minutes. If this is too fast, the input to K1 could be pre-
divided by a second counter.
The AD7224 DAC IC4 lies at the heart of the circuit. This is
a voltage output DAC whose output voltage signal ranges
from zero to the reference voltage on pin 3, which in this
case is the +5 V logic supply voltage. If higher accuracy is
needed, then pin 3 should be fed from a suitable voltage
reference (if an elevated output voltage is required, then
have a look at Application Note AN-316 from Analog
Devices which explains how this can be achieved). The
AD7224 is manufactured by Analog Devices as well as
IC5
78L05
R3
D2
C4
IC2 = 4070B
IC3 = 4070B
100n
1N
C3
C5
16
14
14
4148
T2
100n
100n
IC1
IC2
IC3
IC2.A
=1
1
2
8
7
7
R4
3
2N
2222
IC2.D
=1
12
13
11
18
IC2.B
=1
VDD
5
6
4
17
RESET
9
13
0
D0
CTR12
IC2.C
=1
R1
R2
7
12
IC4
D1
1
D1
8
9
6
10
11
2
D2
3
VREF
5
10
IC1
3
D3
11
3
9
IC3.C
=1
CT=0
4
D4
1N4148
2
8
9
8
5
D5
AD7224
10
CT
10
4
7
+
6
D6
C1
T1
13
6
7
D7
2
IC3.B
=1
12
VOUT
4040
100n
8
5
6
16
14
4
LDAC
9
15
2N
WR
15
C2
VDD
K2
K3
10
14
2222
CS
1
IC3.D
=1
11
100n
AGND
VSS
DGND
12
13
11
4
1
5
GND
<
16V
GND
CLK
IC3.A
=1
K1
1
2
3
014003 - 11
80
Elektor Electronics
12/2001
SMALL CIRCUITS
COLLECTION
to settle first before the counter is incremented.
The whole circuit is powered via K3. Note that the supply
voltage to the AD7224 must be a minimum of 4 V higher
than the reference voltage, up to a maximum of 16 V. See
the AD7224 data sheet for further details.
(014003-1)
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