e011036.PDF
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Pobierz
MICRO
PROCESSOR
Emulator for
27C256 EPROM
with RS232 control
Design by B. Legrand and D. Mautaulon
Going through our
archives we discov-
ered that it’s been
almost ten years
since we published
an EPROM emula-
tor. The version we
propose in this arti-
cle should meet
today’s demands of
hobbyists wishing to
debug microcon-
troller systems
based on an
EPROM. We have
chosen the 27C256
because it is cheap
and currently the
most widely used
EPROM
in
the
hobby area.
36
Elektor Electronics
1/2001
MICRO
PROCESSOR
Technical
features
D0...D7
Buffer
RS232
IC1
A0...A7
A0...A7
IC7
Latch
IC3
Buffer
– Emulates the most widely used
EPROM type 27C256
– RS232 controlled
– Employs HyperTerminal for data
transfer between PC and
EPROM simulator.
– Recognizes industry-standard
IntelHex format
– May be adapted to suit 27C64
and 27C128 by modifying circuit
around pins 26 and 27. Support
for 27C512 also possible with
some hardware and software
modifications.
A8...A14
IC8
A0...A7
A0...A14
RAM
IC5
Processor
IC2
D0...D7
EPROM
IC9
Data
D0...D7
D0...D7
A8...A14
D0...D7
Buffer
Latch
IC4
A8...A14
D0...D6
IC6
D0...D7
000153- 11
Figure 1. Block diagram of the 27C256 EPROM emulator, with the Atmel microcontroller
clearly at the hub of things.
An EPROM emulator is a develop-
ment tool designed to facilitate code
debugging and code writing jobs on
circuits incorporating an EPROM
(electrically erasable read only mem-
ory). An EPROM, as most of you will
know, can not be reprogrammed
before its previous contents has
been erased through exposure to a
certain amount of ultraviolet (UV)
light. So, even for the smallest modi-
fication to the code in your EPROM,
you need to do a complete erase-
and-reprogram cycle, which is
tedious and costly given the time
lost and the price of an UV eraser
box.
An EPROM emulator obviates
these problems by allowing you to
debug, rewrite and download code
as many times as you like, until the
desired system operation is
achieved, all without having to erase
a single EPROM. Having extensively
tested the target program, you need
to program an EPROM just once yet
rest assured that it will work as
planned.
Meanwhile, in this day and age of
Flash reprogrammable and ISP (in-
system programmable) devices, it is
fair to reflect on the advantages, if
any, of an EPROM emulator. Also,
one can not fail to recognise the
trend towards ever larger memory
capacities.
Despite the above trends, there is
still a fair number of circuits based
on microcontrollers running code
from an external EPROM. These con-
trollers include devices from the 8051
series, the 68HC11 and 80C5xx. It is
precisely in this area where the pre-
sent emulator will be highly valued.
microcontroller is used. The main reason for
choosing this device is that it offers on-chip
serial I/O as well as EPROM to store the
firmware that handles the code reception and
control of the emulator.
Practical circuit
Principle of operation
By and large, the circuit diagram shown in
Figure 2
follows the general structure of the
block diagram. In fact, all building blocks dis-
cussed above are fairly easy to find back in
the schematic.
IC1, a MAX232, handles the classic func-
tion of converting the ±10-V signal levels on
the RS232 lines to logic levels (+5 V/0 V), in
two directions. The MAX232 allows the
microcontroller in the circuit to communicate
with the PC via the RS232 port. Although
many PCs these days are capable of handling
serial signals with a swing of 5 V, simply
omitting the MAX232 would require the RxD
and TxD signals to be inverted!
IC2 is the microcontroller type AT89C2051.
It controls latches IC3 and IC4 as well as
buffers IC6, IC7 and IC8. These integrated cir-
cuits ensure the correct interfacing with RAM
IC5. In this context, ‘correct’ means that the
RAM may be accessed by either the micro-
controller or the external (i.e., target) circuit,
but never at the same time.
The RAM in fact emulates (mimics) the
(E)PROM which has been removed form the
target circuit. When the target circuit has
access to the RAM, it will behave as if a sys-
tem (E)PROM was installed, hence the term
‘emulator’. To be able to pull off this trick, the
RAM requires two peripheral devices. From
The block diagram shown in
Fig-
ure 1
is classic and typical for this
type of application.
The underlying principle of an
EPROM emulator is that it replaces
‘dead’ memory like ROM or EPROM
by ‘live’ memory (RAM) with double
(two-port) access. The RAM is
flanked by two latches and sup-
ported by a microcontroller.
As in any EPROM emulator that’s
any good, the heart of the circuit is a
RAM device (here, IC5) which essen-
tially replaces the (E)PROM of the
target (or ‘host’) system. The RAM is
surrounded by latches (IC3 and IC4)
and buffers (IC6, IC7 and IC8). The
exact function of these components
will be discussed a bit further on.
The distinctive feature of the pre-
sent EPROM emulator (as compared
with traditional designs) is the pres-
ence of a microcontroller (IC2). This
component looks after the control of
the latches and the RAM, and also
handles the correct reception (from
the PC) and processing of the object
code to be transferred to the target
system. Here, an Atmel 89AT2051
1/2001
Elektor Electronics
37
MICRO
PROCESSOR
5V
5V
5V
C16
10µ
R2
5V
S1
C10
20
20
20
C15
C6
C4
C8
R8
8x 10k
IC6
IC7
IC8
1
1µ
35V
100n
100n
100n
2
16V
RESET
10
10
10
100n
V+
K1
1
16
R4
D3
C1+
20
C2
1
IC1
IC6
23456789
3
1
10µ
35V
C1–
RST
6
13
14
12
12
13
14
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
9
11
12
13
14
15
16
17
18
DE0
DE1
DE2
DE3
DE4
DE5
DE6
DE7
R1IN
R1OUT
P1.0
P1.1
2
IC2
11
2
3
8
T1OUT
T1IN
P3.0
P3.1
7
8
9
7
R2IN
R2OUT
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
3
7
10
6
7
8
9
6
T2OUT
T2IN
P3.2
P3.3
8
4
5
C14
C2+
4
C1
AT89C2051
4
MAX232A
P3.4
P3.5
9
100n
5
15
3
10µ
35V
C2–
5
V-
2
6
11
C17
P3.7
5V
X1
X2
1
TARGET
5V
&
EN
10µ
35V
5V
10
5
X1
4
19
JP1
1
20
20
C9
C13
74HCT541
IC3
IC4
2
100n
100n
10
10
12MHz
C11
C12
IC10
3
R1
33p
33p
D1
7805
>9V
100mA
1N4001
D2
C7
C3
R5
4k7
R6
4k7
47µ
5V
100n
35V
5V
5V
IC3
IC7
1
&
11
EN
R3
C1
19
1
5V
EN
C5
TARGET
100n
D0
D1
D2
D3
D4
D5
D6
D7
9
12
13
14
15
16
17
18
19
A0
A1
A2
A3
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
18
2
3
4
AE0
AE1
AE2
AE3
AE4
AE5
AE6
AE7
1D
8
17
T1
28
1
28
7
16
VPP
6
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
10
15
5
6
AE0
AE1
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
10
A0
A1
A2
A3
A4
A5
A6
A7
A0
A1
A2
A3
A4
A5
A6
A7
5
9
8
7
6
5
4
3
14
9
8
7
6
5
4
3
BS170
4
13
7
8
9
11
DE0
DE1
DE2
DE3
DE4
DE5
DE6
DE7
D0
3
11
D0
D1
D2
D3
D4
D5
D6
D7
12
D0
IC5
IC9
12
D1
2
12
11
D1
13
D2
13
74HCT573
D2
74HCT541
15
D3
15
IC4
RAM
IC8
EPROM
D3
16
D4
16
1
D4
&
RESET
(L)
11
17
EN
C1
D5
25
17
19
25
A8
D5
A8
27C256
1
18
62256
D6
EN
24
18
24
A9
D6
A9
19
D7
21
23
19
21
23
A10
A11
A12
D7
A10
A11
A12
5V
9
12
13
14
15
16
17
18
19
A8
A9
A10
A11
A12
A13
A14
A15
A14
18
2
3
4
AE14
1D
D0
D1
D2
D3
D4
D5
D6
8
2
A12
A13
17
AE12
AE13
2
R7
20
CS
7
26
16
26
27
A13
A14
A13
A14
6
1
A8
A9
15
5
6
AE8
AE9
RESET
(H)
5
14
OE
WR
CS
OE
4
A11
13
7
8
9
AE11
20
14
22
T2
22
14
27
3
A10
12
AE10
2
11
BS170
74HCT573
74HCT541
000153 - 12
Figure 2. Circuit diagram of the 27C256 EPROM emulator.
one side, the emulator electronics enables the
object code under test to be written into the
RAM, while from the other side the external
(host) system can access the RAM to read
code which the host microcontroller will
eventually execute.
Latches IC3 and IC4 connect the host sys-
tem address lines to the RAM. Depending on
commands received from the microcontroller,
these ICs transfer the data on the internal
databus, D0-D7. Each of the latch enable
inputs is controlled by an individual I/O line
of the central processor. This configuration
allows the processor to control the RAM
address bus. Once the target program is
stored in RAM, the two latches go into high-
impedance mode to avoid contention
problems when the system switches
to emulation mode, i.e., with the
RAM effectively connected into the
target system.
Buffers IC6, IC7 and IC8 ensure
the quasi-connection of the RAM
address and datalines to the exter-
nal (host) circuit.
cuit by means of a mains adapter.
The on-board power supply con-
sists of a three-pin voltage regulator
type 7805 (IC10) in a classic config-
uration. This component provides
the +5-V regulated supply voltage to
the emulator circuitry. Because only
100 mA or so of output current is
required, the 7805 has an unde-
manding job in this circuit. Diode D1
protects the circuit against reverse
polarised input voltages. LED D2
acts as a power on/off indicator.
The second method consists of
powering the emulator from the tar-
get (host) system, which will be pos-
Power supply
The 27C256 EPROM emulator may
be powered in two ways. The first,
which we will treat as the ‘standard’
method, consists of powering the cir-
38
Elektor Electronics
1/2001
MICRO
PROCESSOR
sible in most cases because +5 volts
will be present for the digital cir-
cuitry around the (E)PROM. If you
envisage using this method all the
time, you may omit components
IC10, diode D1 and capacitor C3 from
the emulator circuit.
Jumper JP1 (located near the
voltage regulator) allows you to
select between internal and external
powering.
in its standard application circuit
with four pump capacitors. Sure, we
could have used the SMA version of
the MAX232 and enclosed the com-
plete serial interface in a sub-D con-
nector case for easy connection the
PC. However, to keep construction
as easy as possible we decided to fit
all the parts that make up the inter-
face on the emulator board. This
choice also enables an off the shelf
serial cable to be used.
A note about the RS232 link —
this should consist of a
standard
RS232 cable, i.e., not one with
‘crossed wires’ (also known as
null/zero-modem cable).
tor may be divided into two phases: (1) load-
ing the RAM, and (2) simulating an (E)PROM
in the target system.
For the first task, the PC transmits, via its
serial port, the hexadecimal code to be stored
in the pseudo EPROM. For the second func-
tion, if the target system is to gain access to
the code, it is necessary for the microcon-
troller to pull its port line P3.2 logic Low to
actuate 3-state drivers IC7 and IC8. Two
FETs, T1 and T2, keep the host system in the
reset state.
Let’s see how this works in more detail. At
power-on, the microcontroller, IC2, prepares
all circuitry for data to be written into the
RAM. This is done by pulling all lines of port
P3 to logic High, with the exception of P3.5
and P3.7.
For the microcontroller to get control over
the RAM it has to pull port line P3.2 to logic
High.
The serial link
The communication between the PC
and the emulator consists of two-
way traffic via the RS232 port, for
which suitable circuitry and cable
lines have to be present.
On the emulator board, the RS232
interface consists of a MAX232 (IC1)
How it works
The operation of the EPROM emula-
COMPONENTS LIST
Resistors:
R1,R2 = 1k
Ω
5
R3,R7 = 12k
Ω
R4 = 10k
K1
HOEK1
Ω
R5,R6 = 4k
Ω
7
R8 = 10k
Ω
8-way SIL array
IC2
Capacitors:
C1,C2,C16,C17 = 10
µ
F 35V
C3 =47
µ
F 35V
C4-C9,C13-C15 =100nF
C10 =1
IC4
F 16V
C11,C12 =33pF
µ
IC3
Semiconductors:
D1 = 1N4001
D2,D3 = high efficiency LED
T1,T2 = BS170
IC1 = MAX232 (Maxim)
IC2 = AT89C2051 (Atmel), programmed,
order code
000153-41
IC3,IC4 = 74HCT573
IC5 = 62256 (RAM)
IC6,IC7,IC8 = 74HCT541
IC9 = EPROM being emulated
IC10 = 7805
R1
IC5
R6
IC6
IC7
Miscellaneous:
K1=9-way sub-D socket (female), PCB
mount
PC1-PC4= solder pin
JP1= 3-way SIL pinheader with jumper
S1= pushbutton, 1 make contact
X1=12MHz quartz crystal
PCB, order code 000153-1 (see Readers
Services page)
Disk, project software, order code
000153-
11
(see Readers Services page)
IC9
R5
IC8
HOEK3
Figure 3a. Component mounting plan of the circuit board designed for the 27C256 EPROM emulator.
1/2001
Elektor Electronics
39
MICRO
PROCESSOR
Figure 3b. Copper track layout of the circuit board designed for the 27C256 EPROM emulator. This board is double-sided and through-plated.
To be able to load the RAM, port P1 is sup-
plied with the high address of the first data-
byte. Next, the 3-state driver IC4 is opened
and closed again by means of port line P3.5
in order to block this address.
The above sequence is repeated for the
low address, this time with the aid of port line
P3.7 controlling another 3-state driver, IC3.
Port line P3.2 of the AT89S2015 microcon-
troller is programmed to switch the outputs of
buffers IC6, IC7 and IC8 to high-impedance
(tri-state), which is necessary to ward off all
disturbances caused by the external electron-
ics from the RAM during the write process.
The same signal is also inverted by the
combination T1-R3. The inverted control sig-
nal serves to actuate IC3 and IC4 in such a
way that the RAM address lines are properly
driven. The control signal on P3.2 is put to the
disposal of the target circuit by a pair of sol-
der pins, RESET(L) and RESET(H). One of
these signals may be used to keep the target
system in the reset state while the
RAM is being filed with object code.
Once the complete object code
file has landed in the RAM, the
microcontroller in the emulator pro-
duces a message on the RS232 port.
The PC has to send the object
code file in IntelHex format, via its
RS232 port. The processor on the
emulator board looks after the correct
reception of the file (LED D3 will light
while data is being received from the
PC), and arranges for each databyte
to be written into the RAM at the
proper location. This is achieved by
IC2 copying address lines A0-A7 on
to port P1 and when done producing
a pulse on P3.7. Latch IC3 copies this
word. The same process is repeated
with address group A8-A13. The
data transferred by these addresses
are latched in IC4 when a pulse
appears on port line P3.5. Finally, the
actual databyte is copied on to P1,
followed by a Low pulse produced on
port li
ne P
3.3. The latter drives the
write (WR) input of the RAM. When
a falling pulse edge appears at this
input, the RAM transfers the data-
word on port P1 to the specified
address.
The same procedure is followed
for the transfer of all datawords that
make up the object code.
Once the complete IntelHex file
has been received, the central
processor switches the circuit to
simulation mode. More specifically,
the RAM is switched to read mode
by pulling port line P3.3 Low and
enablin
g th
e RAM output drivers by
pulling OE (output enable) Low. This
is achieved by controlling P3.4.
Pulling P3.3 logic Low also
40
Elektor Electronics
1/2001
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