e009073.pdf

PIC17C75x Instruction Set

Microcontrollers, software

DATASHEET 9/2000

Microcontrollers, software

DATASHEET 9/2000

Mnemonic,

Description

Cycles

16-bit Opcode

Status

Notes

Source:

PIC17C75X Datasheet, Microchip Technology Inc.

Operands

MSb

LSb

Affected

COMF

f,d

Complement f

0001 001d ffff ffff Z

Example Application

PIC Single-Board Computer, Elektor Electronics September 2000

CPFSEQ

Compare f with WREG, skip if f = WREG

1 (2) 0011 0001 ffff ffff None

6,8

CPFSGT

Compare f with WREG, skip if f > WREG

1 (2) 0011 0010 ffff ffff None

2,6,8

CPFSLT

Compare f with WREG, skip if f < WREG

1 (2) 0011 0000 ffff ffff None

2,6,8

Introduction

The PIC17CXXX instruction set consists of 58 instructions. Each instruction is a 16-bit word divided into an

OPCODE and one or more operands. The opcode specifies the instruction type, while the operand(s) further

specify the operation of the instruction. The PIC17CXXX instruction set can be grouped into three types:

– byte-oriented

– bit-oriented

– literal and control operations.

DAW

f,s

Decimal Adjust WREG Register

0010 111s ffff ffff C

DECF

f,d

Decrement f

0000 011d ffff ffff OV,C,DC,Z

DECFSZ

f,d

Decrement f, skip if 0

1 (2) 0001 011d ffff ffff None

6,8

DCFSNZ

f,d

Decrement f, skip if not 0

1 (2) 0010 011d ffff ffff None

6,8

INCF

f,d

Increment f

0001 010d ffff ffff OV,C,DC,Z

INCFSZ

f,d

Increment f, skip if 0

1 (2) 0001 111d ffff ffff None

6,8

INFSNZ

f,d

Increment f, skip if not 0

1 (2) 0010 010d ffff ffff None

6,8

IORWF

f,d

Inclusive OR WREG with f

0000 100d ffff ffff Z

The field descriptions for the opcodes are shown in the first Table. These descriptions are useful for under-

standing the opcodes in the Instruction Set table and in each specific instruction description.

MOVFP

f,p

Move f to p

011p pppp ffff ffff None

MOVPF

p,f

Move p to f

010p pppp ffff ffff Z

MOVWF

Move WREG to f

0000 0001 ffff ffff None

byte-oriented instructions ,

‘f’ represents a file register designator and ‘d’ represents a destination designator. The file register designator

specifies which file register is to be used by the instruction.

The destination designator specifies where the result of the operation is to be placed. If ‘d’ = ‘0’, the result is

placed in the WREG register. If ‘d’ = ‘1’, the result is placed in the file register specified by the instruction.

MULWF

Multiply WREG with f

0011 0100 ffff ffff None

NEGW

f,s

Negate WREG

0010 110s ffff ffff OV,C,DC,Z

1,3

NOP

—

No Operation

0000 0000 0000 0000 None

RLCF

f,d

Rotate left f through Carry

0001 101d ffff ffff C

RLNCF

f,d

Rotate left f (no carry)

0010 001d ffff ffff None

RRCF

f,d

Rotate right f through Carry

0001 100d ffff ffff C

bit-oriented instructions ,

‘b’ represents a bit field designator which selects the number of the bit affected by the operation, while ‘f’ rep-

resents the number of the file in which the bit is located.

RRNCF

f,d

Rotate right f (no carry)

0010 000d ffff ffff None

SETF

f,s

Set f

0010 101s ffff ffff None

SUBWF

f,d

Subtract WREG from f

0000 010d ffff ffff OV,C,DC,Z

SUBWFB

f,d

Subtract WREG from f with Borrow

0000 001d ffff ffff OV,C,DC,Z

literal and control operations ,

‘k’ represents an 8- or 13-bit constant or literal value.

SWAPF

f,d

Swap f

0001 110d ffff ffff None

TABLRD

t,i,f Table Read

2 (3) 1010 10ti ffff ffff None

TABLWT

t,i,f Table Write

1010 11ti ffff ffff None

TLRD

t,f

Table Latch Read

1010 00tx ffff ffff None

The instruction set is highly orthogonal and is grouped into:

– byte-oriented operations

– bit-oriented operations

– literal and control operations

TLWT

t,f

Table Latch Write

1010 01tx ffff ffff None

TSTFSZ

Test f, skip if 0

1 (2) 0011 0011 ffff ffff None

6,8

XORWF

f,d

Exclusive OR WREG with f

0000 110d ffff ffff Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

f,b

Bit Clear f

1000 1bbb ffff ffff None

All instructions are executed within one single instruction cycle, unless:

– a conditional test is true

– the program counter is changed as a result of an instruction

– a table read or a table write instruction is executed (in this case, the execution takes two instruction cycles

with the second cycle executed as a NOP)

BSF

f,b

Bit Set f

1000 0bbb ffff ffff None

BTFSC

f,b

Bit test, skip if clear

1 (2) 1001 1bbb ffff ffff None

6,8

BTFSS

f,b

Bit test, skip if set

1 (2) 1001 0bbb ffff ffff None

6,8

BTG

f,b

Bit Toggle f

0011 1bbb ffff ffff None

LITERAL AND CONTROL OPERATIONS

ADDLW

ADD literal to WREG

1011 0001 kkkk kkkk OV,C,DC,Z

One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 25 MHz, the nor-

mal instruction execution time is 160 ns. If a conditional test is true or the program counter is changed as a

result of an instruction, the instruction execution time is 320 ns.

PIC17C75x Instruction Set

Microcontrollers, software

DATASHEET 9/2000

Microcontrollers, software

DATASHEET 9/2000

OPCODE FIELD DESCRIPTIONS

Field

Description

Mnemonic,

Description

Cycles

16-bit Opcode

Status

Notes

Operands

MSb

LSb

Affected

1 = store result in file register f

Default is s = ‘1’

label Label name

C,DC,Z,OV ALU status bits Carry, Digit Carry, Zero,

Overflow

Field

Description

ANDLW

AND literal with WREG

1011 0101 kkkk kkkk Z

CALL

Subroutine Call

111k kkkk kkkk kkkk None

Peripheral register file address (00h to

1Fh)

CLRWDT

—

Clear Watchdog Timer

0000 0000 0000 0100 TO,PD

GOTO

Unconditional Branch

110k kkkk kkkk kkkk None

Table pointer control i = ‘0’ (do not

change)

i = ‘1’ (increment after instruction execu-

tion)

GLINTD

Global Interrupt Disable bit (CPUS-

TA<4>)

IORLW

Inclusive OR literal with WREG

1011 0011 kkkk kkkk Z

LCALL

Long Call

1011 0111 kkkk kkkk None

4,7

TBLPTR

Table Pointer (16-bit)

MOVLB

Move literal to low nibble in BSR

1011 1000 uuuu kkkk None

MOVLR

Move literal to high nibble in BSR

1011 101x kkkk uuuu None

TBLAT

Table Latch (16-bit) consists of high byte

(TBLATH) and low byte (TBLATL)

Table byte select t = ‘0’ (perform opera-

tion on lower byte)

t = ‘1’ (perform operation on upper byte

literal field, constant data)

MOVLW

Move literal to WREG

1011 0000 kkkk kkkk None

MULLW

Multiply literal with WREG

1011 1100 kkkk kkkk None

TBLATL

Table Latch low byte

RETFIE

—

Return from interrupt (and enable interrupts) 2

0000 0000 0000 0101 GLINTD

TBLATH

Table Latch high byte

RETLW

Return literal to WREG

1011 0110 kkkk kkkk None

TOS

Top of Stack

RETURN

—

Return from subroutine

0000 0000 0000 0010 None

WREG

Working register (accumulator)

Program Counter

SLEEP

—

Enter SLEEP Mode

0000 0000 0000 0011 TO, PD

Bit address within an 8-bit file register

BSR

Bank Select Register

Literal field, constant data or label

SUBLW

Subtract WREG from literal

1011 0010 kkkk kkkk OV,C,DC,Z

Watchdog Timer Counter

WDT

XORLW

Exclusive OR literal with WREG

1011 0100 kkkk kkkk Z

Don’t care location (= ‘0’ or ‘1’)

The assembler will generate code with x

= ‘0’. It is the recommended form of use

for compatibility with all Microchip soft-

ware tools.

Time-out bit

Power-down bit

dest

Destination either the WREG register or

the specified register file location

Notes

1: 2’s Complement method.

2: Unsigned arithmetic.

3: If s = ‘1’, only the file is affected: If s = ‘0’, both the WREG register and the file are affected; If only the

Working register (WREG) is required to be affected, then f = WREG must be specified.

4: During an LCALL , the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkk is loaded

into the LSB of the PC (PCL)

5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The

instruction is terminated by an interrupt event. When writing to external program memory, it is a two-cycle

instruction.

6: Two-cycle instruction when condition is true, else single cycle instruction.

7: Two-cycle instruction except for TABLRD to PCL (program counter low byte) in which case it takes 3

cycles.

8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead an

NOP is executed.

[ ]

Options

Destination select

0 = store result in WREG

1 = store result in file register f

Default is d = ‘1’

( )

Contents

→

Assigned to

< >

∈

In the set of

Unused, encoded as ‘0’

italics

User defined term (font is courier)

Destination select

0 = store result in file register f and in

the WREG

PIC17CXXX INSTRUCTION SET

Mnemonic,

Description

Cycles

16-bit Opcode

Status

Notes

Operands

MSb

LSb

Affected

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

f,d

ADD WREG to f

0000 111d ffff ffff OV,C,DC,Z

ADDWFC f,d

ADD WREG and Carry bit to f

0001 000d ffff ffff OV,C,DC,Z

ANDWF

f,d

AND WREG with f

0000 101d ffff ffff Z

CLRF

f,s

Clear f, or Clear f and Clear WREG

0010 100s ffff ffff None

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