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PAL timing (2)
014
derive a line rate signal from a television frame rate
signal, using a PLL. Naturally, this technique can
also be used in situations where the line synchro-
nization pulses are corrupted.
In the PAL television system, there are 625 lines per
frame. In the PLL circuit, a nominal frequency of
15,625 Hz is thus divided by 625 and then compared
to the 25 Hz input signal. A 74HC4040 (IC2) is
used for the divider. The correct division factor is
obtained with the help of an AND circuit formed
by several diodes, which produces the counter reset
signal (625 decimal = 1001110001 binary).
The well-known HC version of the 4046 IC has
been chosen for the PLL. HC logic must be used
here to keep up with the fast pulse from the output
of the ‘PAL timing (1)’ circuit. Since phase com-
parator 2 is used, the inputs are edge triggered, and
no further requirements need be placed on the
input signals.
As can be seen, the internal oscillator of the PLL
IC is also used (pin 9). The necessary low-pass fil-
ter R3/C2 is not dimensioned entirely according to
the prescribed formulas, but this version proved to
yield the least jitter in practical tests. This brings us directly to the
weak point of this circuit. With a normal RC oscillator, as used
here, it is not possible to reduce the jitter of the 15,625 Hz signal to
5V
C3
C4
R4
100n
100n
15625 Hz
16
D1
9
0
7
16
1
CTR12
6
25 Hz
2
D2
14
VCO
4
10
+
3
5
SIGN
15
ZEN
PLL
CIN
3
4
3
IC2
D3
6
1
2
2
PP
5
CX
IC1
C1
CT
4
P1
P2
6
D4
74HC
74HC4046
13
13
7
8n2
4040
7
11
12
CX
R1
R2
8
CT=0
D5
11
9
14
VCOIN
9
12
DEM
10
R3
10
15
5x
1N4148
1
INH
11
5
8
R1
R2
8
C2
µ
63V
994087 - 11
Design: T. Giesberts
This design is complementary to the design described in the article
‘PAL timing (1)’, which also appears in this issue. It is intended to
48
Elektor Electronics
7-8/99
10
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less than around 200 ns. For most applications, this is not good
enough, so that there is no getting around the use of an external
crystal oscillator for the VCO, in combination with a suitable
divider.
(994087-1)
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