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Xilinx DS311 XC2C64A CoolRunner-II CPLD Data Sheet
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XC2C64A CoolRunner-II CPLD
DS311 (v2.3) November 19, 2008
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Product Specification
A quiescent current
Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
Available in multiple package options
- 44-pin VQFP with 33 user I/Os
- 48-land QFN with 37 user I/Os
- 56-ball CP BGA with 45 user I/Os
- 100-pin VQFP with 64 user I/Os
- Pb-free available for all packages
Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Efficient control term clocks, output enables, and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Optional bus-hold, 3-state, or weak pullup on
selected I/O pins
- Open-drain output option for Wired-OR and LED
drive
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
- PLA architecture
· Superior pinout retention
· 100% product term routability across function
block
- Hot pluggable
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
μ
Description
The CoolRunner-II 64-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved.
This device consists of four Function Blocks inter-connected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configura-
tion bits that allow for combinational or registered modes of
operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain, and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers can be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a
synchronous clock source. Macrocell registers can be indi-
vidually configured to power up to the zero or one state. A
global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset, and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see Ta b l e 1 ). This device is also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II 64A
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
© 2004–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm .
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS311 (v2.3) November 19, 2008
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Product Specification
Features
Optimized for 1.8V systems
- As fast as 4.6 ns pin-to-pin logic delays
- As low as 15
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XC2C64A CoolRunner-II CPLD
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RealDigital Design Technology
Xilinx® CoolRunner-II CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II
CPLDs employ RealDigital, a design technique that makes
use of CMOS technology in both the fabrication and design
methodology. RealDigital design technology employs a cas-
cade of CMOS gates to implement sum of products instead
of traditional sense amplifier methodology. Due to this tech-
nology, Xilinx CoolRunner-II CPLDs achieve both high per-
formance and low power operation.
LVTTL input buffer and Push-Pull output buffer. The
LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applica-
tions. CoolRunner-II CPLDs are also 1.5V I/O compatible
with the use of Schmitt-trigger inputs.
Ta b l e 1 : I/O Standards for XC2C64A
IOSTANDARD
Attribute
Output
V CCIO
Input
V CCIO
Input
V REF
Board
Termination
Voltag e V T
LVTTL
3.3
3.3
N/A
N/A
LVCMOS33
3.3
3.3
N/A
N/A
Supported I/O Standards
The CoolRunner-II 64 macrocell features both LVCMOS
and LVTTL I/O implementations. See Ta b l e 1 for I/O stan-
dard voltages. The LVTTL I/O standard is a general purpose
EIA/JEDEC standard for 3.3V applications that use an
LVCMOS25
2.5
2.5
N/A
N/A
LVCMOS18
1.8
1.8
N/A
N/A
LV C M O S 1 5 (1)
1.5
1.5
N/A
N/A
1. LVCMOS15 requires Schmitt-trigger inputs.
20
15
10
5
0
0
50
100
150
200
250
Frequency (MHz)
DS092_01_092302
Figure 1: I CC vs Frequency
Ta b l e 2 : I CC vs Frequency (LVCMOS 1.8V T A = 25°C) (1)
Frequency (MHz)
0
25
50
75
100
150
175
200
225
240
Typical I CC (mA)
0.017
1.8
3.7
5.5
7.48
11.0
12.7
14.6
15.3
17.77
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block).
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DS311 (v2.3) November 19, 2008
Product Specification
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XC2C64A CoolRunner-II CPLD
Absolute Maximum Ratings
Symbol
Description
Value
Units
V CC
Supply voltage relative to ground
–0.5 to 2.0
V
V CCIO
Supply voltage for output drivers
–0.5 to 4.0
V
V JTAG (2)
JTAG input voltage limits
–0.5 to 4.0
V
V CCAUX
JTAG input supply voltage
–0.5 to 4.0
V
V IN (1)
Input voltage relative to ground (1)
–0.5 to 4.0
V
V TS (1)
Voltage applied to 3-state output (1)
–0.5 to 4.0
V
V STG (3)
Storage Temperature (ambient)
–65 to +150
°C
T J
Junction Temperature
+150
°C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins might undershoot to –2.0V or overshoot to +4.5V, provided this overshoot or undershoot lasts less than 10 ns and
with the forcing current being limited to 200 mA.
2. Valid over commercial temperature range.
3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free
packages, see XAPP427 .
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Units
V CC
Supply voltage for internal logic
and input buffers
Commercial T A = 0°C to +70°C
1.7
1.9
V
Industrial T A = –40°C to +85°C
1.7
1.9
V
V CCIO
Supply voltage for output drivers @ 3.3V operation
3.0
3.6
V
Supply voltage for output drivers @ 2.5V operation
2.3
2.7
V
Supply voltage for output drivers @ 1.8V operation
1.7
1.9
V
Supply voltage for output drivers @ 1.5V operation
1.4
1.6
V
V CCAUX
JTAG programming pins
1.7
3.6
V
DC Electrical Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Typical
Max.
Units
I CCSB
Standby current Commercial
V CC = 1.9V, V CCIO = 3.6V
31
100
μ
A
I CCSB
Standby current Industrial
V CC = 1.9V, V CCIO = 3.6V
43
165
μ
A
I CC (1)
Dynamic current
f = 1 MHz
-
500
μ
A
f = 50 MHz
-
5
mA
C JTAG
JTAG input capacitance
f = 1 MHz
-
10
pF
C CLK
Global clock input capacitance
f = 1 MHz
-
12
pF
C IO
I/O capacitance
f = 1 MHz
-
10
pF
I IL (2)
Input leakage current
V IN = 0V or V CCIO to 3.9V
-
+/–1
μ
A
I IH (2)
I/O High-Z leakage
V IN = 0V or V CCIO to 3.9V
-
+/–1
μ
A
Notes:
1. 16-bit up/down, Resetable binary counter (one counter per function block) tested at V CC =V CCIO = 1.9V.
2. See Quality and Reliability section of the CoolRunner-II family data sheet.
DS311 (v2.3) November 19, 2008
www.xilinx.com
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Product Specification
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XC2C64A CoolRunner-II CPLD
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LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications
Symbol
Parameter
Test Conditions
Min.
Max.
Units
V CCIO
Input source voltage
3.0
3.6
V
V IH
High level input voltage
2
3.9
V
V IL
Low level input voltage
–0.3
0.8
V
V OH
High level output voltage
I OH = –8 mA, V CCIO = 3V
V CCIO – 0.4V
-
V
I OH = –0.1 mA, V CCIO = 3V
V CCIO – 0.2V
-
V
V OL
Low level output voltage
I OL = 8 mA, V CCIO = 3V
-
0.4
V
I OL = 0.1 mA, V CCIO = 3V
-
0.2
V
LVCMOS 2.5V DC Voltage Specifications
Symbol
Parameter
Test Conditions
Min.
Max.
Units
V CCIO
Input source voltage
2.3
2.7
V
V IH
High level input voltage
1.7
V CCIO + 0.3 (1)
V
V IL
Low level input voltage
–0.3
0.7
V
V OH
High level output voltage
I OH = –8 mA, V CCIO = 2.3V
V CCIO – 0.4V
-
V
I OH = –0.1 mA, V CCIO = 2.3V V CCIO – 0.2V
-
V
V OL
Low level output voltage
I OL = 8 mA, V CCIO = 2.3V
-
0.4
V
I OL = 0.1 mA, V CCIO = 2.3V - 0.2 V
1. The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V
without physical damage.
LVCMOS 1.8V DC Voltage Specifications
Symbol
Parameter
Test Conditions
Min.
Max.
Units
V CCIO
Input source voltage
-
1.7
1.9
V
V IH
High level input voltage
-
0.65 x V CCIO
V CCIO + 0.3 (1)
V
V IL
Low level input voltage
-
–0.3
0.35 x V CCIO
V
V OH
High level output voltage
I OH = –8 mA, V CCIO = 1.7V
V CCIO – 0.45
-
V
I OH = –0.1 mA, V CCIO = 1.7V
V CCIO – 0.2
-
V
V OL
Low level output voltage
I OL = 8 mA, V CCIO = 1.7V
-
0.45
V
I OL = 0.1 mA, V CCIO = 1.7V - 0.2 V
1. The V IH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II CPLD input buffer can tolerate up to 3.9V
without physical damage.
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DS311 (v2.3) November 19, 2008
Product Specification
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XC2C64A CoolRunner-II CPLD
LV C M O S 1.5V DC Voltage Specifications
Symbol
Parameter (1)
Test Conditions
Min.
Max.
Units
V CCIO
Input source voltage
-
1.4
1.6
V
V T+
Input hysteresis threshold voltage
-
0.5 x V CCIO
0.8 x V CCIO
V
V T-
-
0.2 x V CCIO
0.5 x V CCIO
V
V OH
High level output voltage
I OH = –8 mA, V CCIO = 1.4V
V CCIO – 0.45
-
V
I OH = –0.1 mA, V CCIO = 1.4V
V CCIO – 0.2
-
V
V OL
Low level output voltage
I OL = 8 mA, V CCIO = 1.4V
-
0.4
V
I OL = 0.1 mA, V CCIO = 1.4V
-
0.2
V
Notes:
1. Hysteresis used on 1.5V inputs.
Schmitt Trigger Input DC Voltage Specifications
Symbol
Parameter
Test Conditions
Min.
Max.
Units
V CCIO
Input source voltage
-
1.4
3.9
V
V T+
Input hysteresis threshold voltage
-
0.5 x V CCIO 0.8 x V CCIO
V
V T-
-
0.2 x V CCIO 0.5 x V CCIO
V
DS311 (v2.3) November 19, 2008
www.xilinx.com
5
Product Specification
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