TDA8540.PDF

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INTEGRATED CIRCUITS
DATA SHEET
4 video switch matrix
Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02
1995 Feb 06
Philips Semiconductors
´
TDA8540
4
376122264.020.png
Philips Semiconductors
Product specification
4
´
4 video switch matrix
TDA8540
FEATURES
·
I 2 C-bus or non-I 2 C-bus mode (controlled by
DC voltages)
·
S-VHS or CVBS processing
·
3-state switches for all channels
·
Selectable gain for the video channels
GENERAL DESCRIPTION
·
sub-address facility
·
Slave receiver in the I 2 C mode
The TDA8540 has been designed for switching between
composite video signals, therefore the minimum of four
input lines are provided as requested for switching
between two S-VHS sources. Each of the four outputs can
be set to a high impedance state, to enable parallel
connection of several devices.
·
Auxiliary logic outputs for audio switching
·
System expansion possible up to 7 devices
(28 sources)
·
Static short-circuit proof outputs
·
ESD protection.
APPLICATIONS
·
Colour Television (CTV) receivers
·
Peritelevision sets
·
Satellite receivers.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V CC
supply voltage
7.2
-
8.8
V
I CC
supply current
-
20
30
mA
I SO
isolation ‘OFF’ state
at f = 5 MHz
60
80
-
dB
B
3 dB bandwidth
12
-
-
MHz
a ct
crosstalk attenuation between
channels
60
70
-
dB
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA8540
DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
TDA8540T
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1995 Feb 06
2
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Philips Semiconductors
Product specification
4
´
4 video switch matrix
TDA8540
BLOCK DIAGRAM
handbook, full pagewidth
V CC(D0,1)
V CC(D2,3)
4
SWITCH MATRIX
15
12
PEAK-
CLAMP
DRIVER
3
3
IN3
GAIN
OUT3
10
PEAK-
CLAMP
DRIVER
2
1
IN2
GAIN
OUT2
IN1
8
PEAK-
CLAMP/
BIAS
GAIN
DRIVER
1
14
OUT1
IN0
6
PEAK-
CLAMP/
BIAS
GAIN
DRIVER
0
16
OUT0
4
4
4
4
2
CL0 to CL1
DECODER
1 OF 4
DECODER
1 OF 4
DECODER
1 OF 4
DECODER
1 OF 4
G0 to G3
4
EN0 to EN3
4
13
20
9
TDA8540
17
2
2
2
2
V CC
D1
D0
DGND
AGND
SUPPLY
I 2 C RECEIVER
2
power reset
11
7
5
18
19
MLA279 - 2
S0
S1
S2
SCL SDA
Fig.1 Block diagram.
1995 Feb 06
3
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Philips Semiconductors
Product specification
4
´
4 video switch matrix
TDA8540
PINNING
SYMBOL PIN
DESCRIPTION
OUT2
1
video output 2
D0
2
control output 0
OUT3
3
video output 3
V CC(D2,3)
4
driver supply voltage; for
drivers 2 and 3
handbook, halfpage
OUT2
1
20
DGND
S2
5
sub-address input 2
IN0
6
video input 0 (CVBS or
chrominance signal)
D0
2
19
SDA
OUT3
3
18
SCL
S1
7
sub-address input 1
V CC(D2,3)
4
17
D1
IN1
8
video input 1 (CVBS or
chrominance signal)
S2
5
16
OUT0
TDA8540
AGND
9
analog ground
IN0
6
15
V CC(D0,1)
IN2
10
video input 2 (CVBS or luminance
signal)
S1
7
14
OUT1
IN1
8
13
V CC
S0
11
sub-address input 0
AGND
9
12
IN3
IN3
12
video input 3 (CVBS or luminance
signal)
IN2
10
11
S0
V CC
13
general supply voltage
MLA277 - 2
OUT1
14
video output 1
V CC(D0,1)
15
driver supply voltage; for
drivers 0 and 1
OUT0
16
video output 0
D1
17
control output 1
SCL
18
serial clock input
SDA
19
serial data input/output
Fig.2 Pinning configuration.
DGND
20
digital ground
1995 Feb 06
4
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Philips Semiconductors
Product specification
4
´
4 video switch matrix
TDA8540
FUNCTIONAL DESCRIPTION
The TDA8540 is controlled via a bidirectional I 2 C-bus.
3 bits of the I 2 C address can be selected via the address
pin, thus providing a facility for parallel connection of
7 devices.
Control options via the I 2 C-bus:
·
Table 1 I 2 C-bus sub-addressing
SUB-ADDRESS
S2
S1
S0
A2
A1
A0
L
L
L
0
0
0
L
L
H
0
0
1
The input signals can be clamped at their negative peak
(top sync).
L
H
L
0
1
0
L
H
H
0
1
1
·
The gain factor of the outputs can be selected between
1
H
L
L
1
0
0
´
or 2
´
.
H
L
H
1
0
1
Each of the four outputs can individually be connected
to one of the four inputs.
· Each output can individually be set in a high impedance
state.
· Two binary output data lines can be controlled for
switching accompanying sound signals.
The SDA and SCL pins (pins 19 and 18) can be connected
to the I 2 C-bus or to DC switching voltage sources. Address
inputs S0 to S2 (pins 11, 7 and 5) are used to select
sub-addresses or switching to the non-I 2 C mode. Inputs
S0 to S2 can be connected to the supply voltage (HIGH) or
the ground (LOW). In this way no peripheral components
are required for selection.
H
H
L
1
1
0
H
H
H
non I 2 C addressable
I 2 C-bus control
After power-up the outputs are initialized in the high
impedance state, and D0 and D1 are at a LOW level.
Detailed description of the I 2 C-bus specification, with
applications, is given in brochure “The I 2 C-bus and how to
use it”. This brochure may be ordered using the code
9398 393 40011.
The TDA8540 is a slave receiver and the protocol is given
in Table 2.
Table 2 The TDA8540 protocol
SEQUENCE
S (1)
SLV (2)
A (3)
SUB
A (3)
DATA
A (3)
DATA
A (3)
P (4)
Notes
1. S = START condition.
2. Data transmission to the TDA8540 starts with the slave address (SLV).
3. A = acknowledge bit, generated by TDA8540.
4. P = STOP condition.
Table 3 Data transmission to the TDA8540 begins with SLV
A6
MSB
A5
A4
A3
A2
A1
A0
R/W
LSB
1
0
0
1
A2 (1)
A1 (1)
A0 (1)
0 (2)
Notes
1. A 2 t o A0: pin programmable slave address bits.
2. R/W = 0; write only.
After the SLV, a second byte, SUB, is required for selecting the functions, as shown in Table 4.
1995 Feb 06
5
·
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