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WIDE BANDWIDTH SINGLE J-FET OPERATIONAL AMPLIFIERS
LF155-LF255-LF355
LF156-LF256-LF356
LF157-LF257-LF357
WIDE BANDWIDTH
SINGLE J-FET OPERATIONAL AMPLIFIERS
. HIGH INPUT IMPEDANCE J-FET INPUT
STAGE
. OFFSET VOLTAGE ADJUSTMENT DOES NOT
DEGRADE DRIFT OR COMMON-MODE
REJECTION AS IN MOST OF MONOLITHIC
AMPLIFIERS
s
. INTERNAL COMPENSATION AND LARGE
DIFFERENTIAL INPUT VOLTAGECAPABILITY
(UP TO V CC + )
N
DIP8
(Plastic Package)
D
SO8
(Plastic Micropackage)
. PRECISION HIGH SPEED INTEGRATORS
. WIDEBAND, LOW NOISE, LOW DRIFT
ORDER CODES
. LOGARITHIMIC AMPLIFIERS
Part Number
Temperature
Range
Package
ND
. PHOTOCELL AMPLIFIERS
LF355, LF356, LF357
0 o C, +70 o C
••
. SAMPLE AND HOLD CIRCUITS
LF255, LF256, LF257 –40 o C, +105 o C
••
LF155, LF156, LF157 –55 o C, +125 o C
••
Example : LF355N
PIN CONNECTIONS (top view)
1
8
DESCRIPTION
These circuits are monolithic J-FET input operational
amplifiers incorporating well matched, high voltage
J-FET on the same chip with standard bipolar transis-
tors.
This amplifiers feature low input bias and offset cur-
rents, low input offset voltage and input offset voltage
drift, coupledwith offset adjust which doesnot degrade
drift or common-mode rejection.
The devices are also designed for high slew rate, wide
bandwidth,extremelyfast settling time, lowvoltageand
current noise and a low 1/f noise level.
2
7
3
6
4
5
1 - Offset Null 1
2 - Inverting input
3 - Non-inverting input
4-V CC -
5 - Offset Null 2
6 - Output
7-V CC +
8 - N.C.
October 1997
1/14
. HIGH SPEED J-FET OP-AMPs : up to 20MHz,
50V/
m
TYPICAL APPLICATIONS
. FAST D/A AND CONVERTERS
. HIGH IMPEDANCE BUFFERS
AMPLIFIERS
311389604.002.png
LF155 - LF156 - LF157
SCHEMATIC DIAGRAM
V io ADJUSTMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V CC
Supply Voltage
±
2
V
V i
Input Voltage - (note 1)
± 20
V
V id
Differential Input Voltage
40
V
P tot
Power Dissipation
570
mW
Output Short-circuit Duration
Infinite
T oper
Operating Free Air Temperature Range
LF155-LF156-LF157
LF255-LF256-LF257
LF355-LF356-LF357
-55 to +125
–40 to +105
0to70
o C
T stg
Storage Temperature Range
–65 to 150
o C
2/14
±
311389604.003.png
LF155 - LF156 - LF157
ELECTRICAL CHARACTERISTICS
LF155, LF156, LF157
-55 o C 3
T amb
3
+125 o C
± 5V 3
V CC
3 ± 20V
LF255, LF256, LF257
-40 o C
3
T amb
3
+105 o C
±
5V
3
V CC
3 ±
20V
(unless otherwise specified)
Symbol
Parameter
LF155 - LF156 - LF157
LF255 - LF256 - LF257
Unit
Min.
Typ.
Max.
V io
Input Offset Voltage (R S =50 W )
T amb =25 o C
T min.
mV
3
5
7
6.2
3
T amb
3
T max.
LF155, LF156, LF157
LF255, LF256, LF257
I io
Input Offset Current - (note 3)
T amb =25 o C
T min.
3
20
20
1
pA
nA
nA
3
T amb
3
T max.
LF155, LF156, LF157
LF255, LF256, LF257
I ib
Input Bias Current - (note 3)
T amb =25 o C
T min.
20
100
50
5
pA
nA
nA
3
T amb
3
T max.
LF155, LF156, LF157
LF255, LF256, LF257
A vd
Large Signal Voltage Gain (R L =2k
W
,V O =
±
10V, V CC =
±
15V)
V/mV
50
25
200
3
T amb
3
T max.
SVR
Supply Voltage Rejection Ratio - (note 4)
85
100
dB
I CC
Supply Current (V CC =
±
15V, no load)
mA
LF155, LF255
LF156, LF256
LF157, LF257
2
5
5
4
7
7
DV io
Input Offset Voltage Drift (R S =50
W
)
5
m
V/ o C
DV io /V io Change in Average Temperature Coefficient with V io adjust
(R S =50
0.5
m
V/ o C
W
) - (note 2)
V icm
Input Common Mode Voltage Range (V CC =
±
15V, T amb =25 o C)
±
11
+15.1
-12
V
CMR
Common Mode Rejection Ratio
85
100
dB
±
V OPP Output Voltage Swing (V CC =
±
15V)
V
R L = 10k
W
±
12
±
13
R L =2k
W
±
10
±
12
GBP
Gain Bandwidth Product (V CC =
±
15V, T amb =25 o C)
LF155, LF255
LF156, LF256
LF157, LF257
MHz
2.5
5
20
SR
Slew Rate (V CC =
15V, T amb =25 o C)
V/
m
s
A V = 1
LF155, LF255
LF156, LF256
5
12
50
7.5
30
A V = 5
LF157, LF257
R i
Input Resistance (T amb =25 o C)
10 12
W
C i
Input Capacitance (V CC =
±
15V, T amb =25 o C)
3
pF
e n
Equivalent Input Noise Voltage
(V CC =
15V, T amb =25 o C, R S = 100
nV
/```
±
W
)
Hz
f = 1000Hz
LF155, LF255
LF156, LF256
LF157, LF257
20
12
12
25
15
15
f = 100Hz
LF155, LF255
LF156, LF256
LF157, LF257
i n
Equivalent Input Noise Current
(V CC = ± 15V, T amb =25 o C, f = 100Hz or f = 1000Hz)
0.01
pA
/```
Hz
t s
Settling Time (V CC =
±
15V, T amb =25 o C) - (note 5)
LF155, LF255
LF156, LF256
LF157, LF257
m
s
4
1.5
1.5
3/14
T amb =25 o C
T min.
T amb =25 o C
±
311389604.004.png
LF155 - LF156 - LF157
ELECTRICAL CHARACTERISTICS
LF355, LF356, LF357
0 o C
3
T amb
3
+70 o C
V CC = ± 15V , (unless otherwise specified)
Symbol
Parameter
LF355 - LF356 - LF357
Unit
Min.
Typ.
Max.
V io
Input Offset Voltage (R S =50
W
)
mV
3
10
13
3
T amb
3
T max.
I io
Input Offset Current - (note 3)
T amb =25 o C
T min.
3
50
2
pA
nA
3
T amb
3
T max.
I ib
Input Bias Current - (note 3)
T amb =25 o C
T min.
20
200
8
pA
nA
3
T amb
3
T max.
A vd
Large Signal Voltage Gain (R L =2k
W
,V O =
±
10V)
V/mV
25
15
200
3
T amb
3
T max.
SVR
Supply Voltage Rejection Ratio - (note 4)
80
100
dB
I CC
Supply Current (no load)
T amb =25 o C
LF355
LF356, LF357
2
5
4
10
mA
DV io
Input Offset Voltage Drift (R S =50
W
) - (note 2)
5
m
V/ o C
DV io /V io Change in Average Temperature Coefficient with V io adjust
(R S =50
W
)
0.5
V/ o C
per mV
V icm
Input Common Mode Voltage Range (T amb =25 o C)
±
10
+15.1
-12
V
CMR
Common Mode Rejection Ratio
80
100
dB
±
V OPP Output Voltage Swing
R L = 10k
W
±
12
±
13
V
R L =2k
W
±
10
±
12
Gain Bandwidth Product T amb =25 o C)
GBP
LF355
LF356
LF357
2.5
5
20
MHz
SR
Slew Rate (T amb =25 o C)
A V = 1
V/
m
s
LF355
LF356
5
12
50
A V = 5
LF357
R i
Input Resistance (T amb =25 o C)
10 12
W
C i
Input Capacitance (Tamb = 25 o C)
3
pF
e n
Equivalent Input Noise Voltage (T amb =25 o C, R S = 100
W
)
nV
/```
f = 1000Hz
LF355
LF356, LF357
20
12
25
15
Hz
f = 100Hz
LF355
LF356, LF357
i n
Equivalent Input Noise Current
(T amb =25 o C, f = 100Hz or f = 1000Hz)
0.01
pA
/```
Hz
t s
Settling Time (T amb =25 o C) - (note 5)
LF355
LF356, LF357
4
1.5
m
s
Notes : 1. Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
2. The temperature coefficient of the adjusted input offset voltage changes only a small amount (0.5
V/ o C typically) for each mV
of adjustment from its original unadjusted value. Common-mode rejection and open loop voltage gain are alsounaffected by
offset adjustment.
3. The input bias currents are junction leakage currents which approximately double for every 10 o C increase in the junction
temperature T amb . Due to limited production test time, the input bias current measured is correlated to junction temperature.
In a normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation,
P tot -T amb =T amb +R th(j-a) xP tot where Rt h(j-a) is the thermal resistance from junction to ambient. Use of a heatsink is recommended
f input currents are to be kept to a minimum.
4. Supply voltage rejection is measured for both supply magnitudes increasing or decreasing simultaneously, in accordance with
common practise.
5. Settling time is defined here, for a unity gain inverter connection using 2k
m
resistors for the LF155, LF156 series. It is the time
required for the error voltage (the voltage at the inverting input pin on the amplifier) to settle to within 0.01% of its final value from
the time a 10V step input is applied to the inverter. For the LF157 series A V = -5, the feedback resistor from output to input is 2k
W
W
and the output step is 10V.
4/14
T amb =25 o C
T min.
T amb =25 o C
T min.
m
311389604.005.png
LF155 - LF156 - LF157
APPLICATION HINTS
The LF155, LF156, LF157 series are op amps with J-
FETinput transistors. TheseJFETs havelarge reverse
breakdown voltagesfromgateto source or drain elimi-
natingtheneed of clamps across the inputs. Therefore
large differential input voltages can easily be accom-
modatedwithouta large increaseof inputcurrents. The
maximum differential input voltage is independent of
the supply voltage. However, neitherof thenegative in-
put voltagesshould be allowed to exceedthe negative
supply as this will cause large currents to flow which
can result in a destroyed unit. Exceeding the negative
common-mode limit on either inputwill causeareversal
of thephaseto theoutputandforce the amplifier output
to the correspondinghigh or lowstate. Exceedingthe
negativecommon-mode limit on bothinputs will force
the amplifier outputto a high state. In neithercase does
a latch occur since raising the input back within the
common-mode range again puts the input stage and
thusthe amplifier in a normal operating mode. Exceed-
ingthepositive common-modelimit on asingle input will
not changethe phase of the output however, if bothin-
putsexceedthe limit, theoutput of theamplifier will be
forced to a high state. These amplifiers will operatewith
the common-mode input voltage equal to the positive
supply. In fact, the common-modevoltagecanex-
ceedthepositivesupplyby approximately 100 mV inde-
pendentof supply volt-age and over thefull operat-
ingtemperaturerange.The positive suplly can there-
forebe used as a referenceon an input as, forexample,
in a supply current monitor and/or limiter. Precautions-
should be taken to ensurethat the powersupply for the
integrated circuit never becomes re-versed in polarity
or that the unit is not inadvertentlyin-stalled backwards
in a socket as an unilimited current surge throughthe
resulting forward diode within the IC couldcausefusin-
gof theinternalconductorsandresultin a destroyedunit.
Because these amplifiers are JFET rather than MOS-
FET input op amps they do not require special han-
dling.
Allof the biascurrentsin these amplifiersareset by FET
current sources. The drain currents for the amplifiers
are therefore essentially independent of supply volt-
ages.
As with most amplifiers, care should betaken with lead
dress, components placement and supply decoupling
in order to ensure stability. For example, resistors from
the output to an input should be placed with the body
close to theinput to minimiz ”pickup” and maximize the
frequency of the feedback pole by minimizing the ca-
pacitancefrom the input to ground.
A feedback pole is createdwhen the feedbackaround
any amplifier is resistive. The parallel resistance and
capacitancefromthe input of thedevice(usually the in-
vertinginput)toacgroundsetthefrequencyofthepole. In
many instances the frequency of this pole is much
greaterthanthe expected3 dBfrequencyof the closed
loopgain and consequentlythereisnegligible effect on
stability margin. However, if the feedback pole is less
than approximately six time the expected 3 dB fre-
quencya leadcapacitor should be placed from the out-
put to the input of the op amp. The value of that added
capacitor should be such that the RC time constant of
this capacitor and the resistance it parallels is greater
than or equal to the original feedback pole time con-
stant.
5/14
311389604.001.png

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