ATiny13.pdf

Features

High Performance, Low Power AVR ® 8-Bit Microcontroller

Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Througput at 20 MHz

Non-volatile Program and Data Memories

– 1K Byte of In-System Programmable Program Memory Flash

Endurance: 10,000 Write/Erase Cycles

– 64 Bytes In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– 64 Bytes Internal SRAM

– Programming Lock for Self-Programming Flash Program and EEPROM Data

Security

Peripheral Features

– One 8-bit Timer/Counter with Prescaler and Two PWM Channels

– 4-channel, 10-bit ADC with Internal Voltage Reference

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, and Power-down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

I/O and Packages

– 8-pin PDIP/SOIC: Six Programmable I/O Lines

– 20-pad MLF: Six Programmable I/O Lines

Operating Voltage:

– 1.8 - 5.5V for ATtiny13V

– 2.7 - 5.5V for ATtiny13

Speed Grade

– ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

Industrial Temperature Range

Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 240µA

– Power-down Mode:

< 0.1µA at 1.8V

8-bit

Microcontroller

with 1K Bytes

In-System

Programmable

Flash

ATtiny13V

ATtiny13

Rev. 2535G–AVR–01/07

2535G–AVR–01/07

Pin Configurations

Figure 1. Pinout ATtiny13

PDIP/SOIC

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

(PCINT4/ADC2) PB4

GND

VCC

PB2 (SCK/ADC1/T0/PCINT2)

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

QFN/MLF

(PCINT5/RESET/ADC0/dW) PB5

(PCINT3/CLKI/ADC3) PB3

DNC

(PCINT4/ADC2) PB4

VCC

PB2 (SCK/ADC1/T0/PCINT2)

DNC

PB1 (MISO/AIN1/OC0B/INT0/PCINT1)

PB0 (MOSI/AIN0/OC0A/PCINT0)

NOTE: Bottom pad should be soldered to ground.

DNC: Do Not Connect

Overview

The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the

ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

ATtiny13

2535G–AVR–01/07

ATtiny13

Block Diagram

Figure 2. Block Diagram

8-BIT DATABUS

STACK

POINTER

CALIBRATED

WATCHDOG

OSCILLATOR

INTERNAL

OSCILLATOR

SRAM

WATCHDOG

TIMER

TIMING AND

CONTROL

VCC

PROGRAM

COUNTER

MCU CONTROL

GND

MCU STATUS

PROGRAM

FLASH

TIMER/

COUNTER0

INSTRUCTION

GENERAL

PURPOSE

REGISTERS

INTERRUPT

UNIT

PROGRAMMING

LOGIC

INSTRUCTION

DECODER

CONTROL

LINES

ALU

DATA

EEPROM

STATUS

ADC /

ANALOG COMPARATOR

DATA REGISTER

PORT B

DATA DIR.

REG.PORT B

PORT B DRIVERS

RESET

CLKI

PB0-PB5

2535G–AVR–01/07

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers.

The ATtiny13 provides the following features: 1K byte of In-System Programmable

Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general pur-

pose working registers, one 8-bit Timer/Counter with compare modes, Internal and

External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with

internal Oscillator, and three software selectable power saving modes. The Idle mode

stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and

Interrupt system to continue functioning. The Power-down mode saves the register con-

tents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC

Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize

switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology.

The On-chip ISP Flash allows the Program memory to be re-programmed In-System

through an SPI serial interface, by a conventional non-volatile memory programmer or

by an On-chip boot code running on the AVR core.

The ATtiny13 AVR is supported with a full suite of program and system development

tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-

cuit Emulators, and Evaluation kits.

Pin Descriptions

VCC

Digital supply voltage.

GND

Ground.

Port B (PB5..PB0)

Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny13 as listed on

page 51.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

12 on page 31. Shorter pulses are not guaranteed to generate a reset.

About Code

Examples

This documentation contains simple code examples that briefly show how to use various

parts of the device. These code examples assume that the part specific header file is

included before compilation. Be aware that not all C compiler vendors include bit defini-

tions in the header files and interrupt handling in C is compiler dependent. Please

confirm with the C compiler documentation for more details.

ATtiny13

2535G–AVR–01/07

ATtiny13

AVR CPU Core

Introduction

This section discusses the AVR core architecture in general. The main function of the

CPU core is to ensure correct program execution. The CPU must therefore be able to

access memories, perform calculations, control peripherals, and handle interrupts.

Architectural Overview

Figure 3. Block Diagram of the AVR Architecture

Data Bus 8-bit

Flash

Program

Memory

Program

Counter

Status

and Control

Instruction

32 x 8

General

Purpose

Registrers

Interrupt

Unit

Instruction

Decoder

Watchdog

Timer

ALU

Analog

Comparator

Control Lines

I/O Module1

Data

SRAM

I/O Module 2

I/O Module n

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture

– with separate memories and buses for program and data. Instructions in the Program

memory are executed with a single level pipelining. While one instruction is being exe-

cuted, the next instruction is pre-fetched from the Program memory. This concept

enables instructions to be executed in every clock cycle. The Program memory is In-

System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with

a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)

operation. In a typical ALU operation, two operands are output from the Register File,

2535G–AVR–01/07

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