u4083b.pdf

U4083B

Low-Power Audio Amplifier for Telephone Applications

Description

The integrated circuit, U4083B, is a low-power audio

amplifier for telephone loudspeakers. It has differential

speaker outputs to maximize the output swing at low

supply voltages. There is no need for coupler capacitors.

The U4083B has an open loop gain of 80 dB whereas the

closed loop gain is adjusted with two external resistors.

A chip disable pin permits powering down and/or muting

the input signal.

Wide operating voltage range: 2 to 16 V

Output power, P o = 250 mW @ R L = 32 (speaker)

Battery-powered application due to low quiescent

supply current: 2.7 mA typical

Low harmonic distortion (0.5% typical)

Wide gain range: 0 dB to 46 dB

Chip disable input to power down the integrated

circuit

Benefits

Low power-down quiescent current

Low number of external components

Drives a wide range of speaker loads

Low current consumption

Block Diagram / Application Circuit

75 k

R f

V S

0.1 F

R i

V i

Amp.1

–

Input

3 k

C i

VO1

FC1

4 k

1 F

C 1

50 k

5 F

–

1 2 5 k

VO2

Amp.2

C 2

FC2

50 k

Bias

circuit

93 7781 e

GND

Figure 1. Block diagram/ application circuit

Order Information

Extended Type Number

Package

Remarks

U4083B-AFP

SO8

Tube

U4083B-AFPG3

SO8

Taped and reeled

Rev. A3, 01-Jun-99

1 (11)

Features

U4083B

Pin Description

VO2

Pins 2 and 3: Filtering, power supply rejection

Power supply rejection is provided by capacitors C 1 and

C 2 at Pin 3 and Pin 2, respectively. C 1 is dominant at high

frequencies whereas C 2 is dominant at low frequencies

(figures 4 to 7). The values of C 1 and C 2 depend on the

conditions of each application. For example, a line-

powered speakerphone (telephone amplifier) will require

more filtering than a system powered by regulated power

supply.

The amount of rejection is a function of the capacitors and

the equivalent impedance at Pin 3 and Pin 2 (see electrical

characteristic equivalent resistance, R).

FC2

GND

FC1

V S

V i

VO1

94 8022

Figure 2. Pinning

Apart from filtering, capacitors C 1 and C 2 also influence

the turn-on time of the circuit at power-up since capaci-

tors are charged up through the internal resistors (50 k

and 125 k) as shown in the block diagram.

Symbol

Function

Chip disable

FC2

Filtering, power supply rejection

FC1

Filtering, power supply rejection

Figure 1 shows turn-on time versus C 2 at V S = 6 V, for

two different C 1 values.

Turn-on time is 60% longer when V S = 3 V and 20%

shorter when V S = 9 V.

Turn-off time is less than 10 s

V i

Amplifier input

VO1

Amplifier output 1

V S

Voltage supply

GND

Ground

VO2

Amplifier output 2

Pin 4: Amplifier input V i

Pin 5: Amplifier output 1 V O1

Pin 8: Amplifier output 2 V O2

There are two identical operational amplifiers. Amp.1 has

an open-loop gain 80 dB at 100 Hz (figure 2), whereas

the closed-loop gain is set by external resistors, R f and R i

(figure 3). The amplifier is unity gain stable, and has a

unity gain frequency of approximately 1.5 MHz. A

closed-loop gain of 46 dB is recommended for a

frequency range of 300 to 3400 Hz (voice band). Amp.2

is internally set to a gain of –1.0 (0 dB). The outputs of

both amplifiers are capable of sourcing and sinking a peak

current of 200 mA. Output voltage swing is between 0.4

V and V s – 1.3 V at maximum current (figures 18 and 19).

The output dc offset voltage between Pins 5 and 8 (V O1

– V O2 ) is mainly a function of the feedback resistor, R f ,

because the input offset voltage of the two amplifiers

neutralize each other.

Bias current of Amp. 1 which is constant with respect to

V s , however, flows out of Pin 4 (V i ) and through R f ,

forcing V 01 to shift negative by an amount equal to R f I IB

and V O2 positive to an equal amount.

The output offset voltage specified in the electrical char-

acteristics is measured with the feedback resistor

(R f = 75 k) shown in typical application circuit. It takes

into account bias current as well as internal offset voltages

of the amplifiers.

Functional Description

Including External Circuitry

Pin 1: Chip disable digital input (CD)

Pin 1 (chip disable) is used to power down the IC to con-

serve power or muting or both.

Input impedance at Pin 1 is typically 90 k.

Logic 0 < 0.8 V IC enabled (normal operation)

Logic 1 > 2 V IC disabled

Figure 15 shows the power supply current diagram. The

change in differential gain from normal operation to

muted operation (muting) is more than 70 dB.

Switching characteristics are as follows:

turn-on time t on = 12 to 15 ms

turn-off time t off 2 s

They are independent of C 1 , C 2 and V S .

Voltages at Pins 2 and 3 are supplied from V S and there-

fore do not change when the U4083B is disabled. Outputs

V O1 (Pin 5) and V O2 (Pin 8) turn to a high imped-

ance condition by removing the signal from the speaker.

When signals are applied from an external source to the

outputs (disabled), they must not exceed the range

between the supply voltage, V S , and ground.

2 (11)

Rev. A3, 01-Jun-99

U4083B

Pin 6: Supply and power dissipation

The IC’s operating range is defined by a peak operating

load current of 200 mA (figures 8 to 13). It is further

specified with respect to different loads (see figure 14).

The left (ascending) portion of each of the three curves is

defined by the power level at which 10% distortion

occurs. The center flat portion of each curve is defined by

the maximum output current capability of the integrated

circuit. The right (descending) portion of each curve is

defined by the maximum internal power dissipation of the

IC at 25

Power dissipation is shown in figures 8 to 10 for different

loads. Distortion characteristics are given in figures 11 to

13.

P totmax

T jmax –T amb

R thJA

where

T jmax = Junction temperature = 140

C. At higher ambient temperatures, the

maximum load power must be reduced according to the

above mentioned equation.

Layout Considerations

T amb = Ambient temperature

R thJA = Thermal resistance, junction-ambient

Power dissipated within the IC in a given application is

found from the following equation:

Normally, a snubber is not needed at the output of the IC,

unlike many other audio amplifiers. However, the PC

board layout, stray capacitances, and the manner in which

the speaker wires are configured, may dictate otherwise.

Generally, the speaker wires should be twisted tightly, and

be not more than a few cm (or inches) in length.

P tot = (V S I S ) + (I RMS V S ) – (R L I RMS 2 )

I S is obtained from figure 15

I RMS is the RMS current at the load R L.

Absolute Maximum Ratings

Reference point Pin 7, T amb = 25

C unless otherwise specified.

Parameters

Symbol

Value

Unit

Supply voltage

Pin 6

V S

–1.0 to +18

Voltages

Pins 1, 2, 3 and 4

–1.0 to (VS +1.0)

Disabled

Pins 5 and 8

Output current

Pins 5 and 8

250

Junction temperature

T j

+140

Storage temperature range

T stg

–55 to +150

Ambient temperature range

T amb

–20 to +70

Power dissipation: T amb = 60

SO8

P tot

440

Thermal Resistance

Parameters

Symbol

Value

Unit

Junction ambient

SO8

R thJA

180

K/W

Operation Recommendation

Parameters

Symbol

Value

Unit

Supply voltage

Pin 6

V S

2 to 16

Load impedance

Pins 5 to 8

R L

8.0 to 100

Load current

I L

200

Differential gain (5.0 kHz bandwidth)

0 to 46

Voltage @ CD Pin 1

V CD

Ambient temperature range

T amb

–20 to +70

Rev. A3, 01-Jun-99

3 (11)

U4083B

Electrical Characteristics

T amb = +25

C, reference point Pin 7, unless otherwise specified

Parameters

Test Conditions / Pins

Symbol Min.

Typ.

Max.

Unit

Amplifiers (AC Characteristics)

Open-loop gain

(Amp. 1, f < 100 Hz)

G VOL1

Closed-loop gain (Amp. 2)

V S = 6.0 V, f = 1.0 kHz, R L = 32

G V2

–0.35

+0.35

Gain bandwidth product

G BW

1.5

MHz

Output power

V S = 3.0 V, R L = 16 , d < 10%

V S = 6.0 V, R L = 32 , d < 10%

V S = 12 V, R L = 100 , d < 10%

250

400

Total harmonic distortion

(f = 1.0 kHz)

V S = 6.0 V, R L = 32 ,

P o = 125 mW

V S > 3.0 V, R L = 8 ,

P o = 20 mW

V S > 12 V, R L = 32 ,

P o = 200 mW

0.5

1.0

0.5

0.6

Power supply rejection

ratio

V S = 6.0 V, V S = 3.0 V

C 1 = , C 2 = 0.01 F

C 1 = 0.1 F, C 2 = 0, f = 1.0 kHz

C 1 = 1.0 F, C 2 = 5.0 F,

f = 1.0 kHz

PSRR

Muting

V S = 6.0 V, 1.0 kHz < f < 20 kHz,

CD = 2.0 V

G MUTE

>70

Amplifiers (DC Characteristics)

Output DC level at V O1 ,

V O2

R f = 75 kW

V S = 3.0 V, R L = 16

V S = 6.0 V

V S = 12 V

V O

1.0

1.15

2.65

5.65

1.25

Output high level

I O = – 75 mA,

2.0 V < V S < 16 V

V OH

V S –1

Output low level

I O = 75 mA,

2.0 V < V S < 16 V

V OL

0.16

Output DC offset voltage

(V O1 – V O2 )

V S = 6.0 V, R f = 75 k,

R L = 32

V O

–30

+30

Input bias current at V i

V S = 6.0 V

–I IB

100

200

Equivalent resistance at

Pin 3

V S = 6.0 V

100

150

220

Equivalent resistance at

Pin 2

V S = 6.0 V

Chip disable Pin 1

Input voltage low

Input voltage high

Input resistance

V IL

V IH

R CD

0.8

V S = V CD = 16 V

2.0

175

Power supply current

V S = 3.0 V, R L = , CD = 0.8 V

V S = 16 V, R L = , CD = 0.8 V

V S = 3.0 V, R L = , CD = 2.0 V

I S

4.0

5.0

100

4 (11)

Rev. A3, 01-Jun-99

U4083B

Typical Temperature Performance

T amb = –20 to +70

Function

Typical Change

Units

Input bias current at V i

pA/

Total harmonic distortion

V S = 6.0 V, R L = 32 , P o = 125 mW,

f = 1.0 kHz

+ 0.003

Power supply current

V S = 3.0 V, R L = , CD = 0 V

V S = 3.0 V, R L = , CD = 2.0 V

– 2.5

– 0.03

360

R f = 150 k

R i = 6 k

300

C 1 = 5 F

R f = 75 k

R i = 3 k

240

R f

180

Input

C i

R i

V O1

120

0.1 F

1 F

Amp 1

Outputs

V O2

V S switching from 0 to + 6 V

Amp 2

100

94 7838 e

C 2 ( F )

93 7797 e

Frequency ( kHz )

Figure 1. Turn-on time vs. C 1 , C 2 at power on

Figure 3. Differential gain vs. frequency

100

99.33

C 1 1 F

Phase

92.67

C 1 = 0.1 F

86.00

C 2 = 10 F

79.33

Gain

C 1 = 0

72.67

66.00

0.1

100

1000

0.1

100

94 7839 e

f ( kHz )

93 7798 e

f ( kHz )

Figure 2. Amplifier 1 – open-loop gain and phase

Figure 4. Power supply rejection vs. frequency

Rev. A3, 01-Jun-99

5 (11)

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