tp3155.pdf

September 1993

TP3155 Time Slot Assignment Circuit

General Description

The TP3155 is a monolithic CMOS logic circuit designed to

generate transmit and receive frame synchronization pulses

for up to 8 COMBO TM CODEC/Filters. Each frame sync

pulse may be independently assigned to a time slot in a

frame of up to 32 time slots. Assignments are controlled by

loading in an 8-bit word via a simple serial interface port.

This control interface is compatible with that used on the

TP3020/TP3021 and 2910/2911 CODECs, enabling an

easy upgrade to COMBO CODEC/Filters to be made.

Features

Y Controls up to 8 COMBO CODEC/Filters

Y Independent transmit and receive time slot assignments

Y 8-channel unidirectional mode

Y Up to 32 time slots per frame

Y Serial control interface compatible with TP3020/TP3021

CODECs

Y LS TTL and CMOS compatible inputs

Y 5 mW, 5V operation

Typical Application

TL/H/5118±1

TRI-STATE É is a registered trademarks of National Semiconductor Corp.

COMBO TM is a trademark of National Semiconductor Corp.

C 1995 National Semiconductor Corporation

TL/H/5118

RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

V CC Relative to GND

Operating Temperature Range

(Ambient)

b 25 § Cto a 125 § C

Storage Temperature Range

(Ambient)

b 65 § Cto a 150 § C

Voltage at Any Input

or Output

V CC a 0.3V to GND b 0.3V

Maximum Lead Temperature

(Soldering, 10 seconds)

300 § C

ESD rating to be determined.

DC Electrical Characteristics

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC e 5.0V g 5%; T A e 0 § Cto a 70 § Cby

correlation with 100% electrical testing at T A e 25 § C. All other limits are assured by correlation with other production tests and/

or product design and characterization. Typicals specified at V CC e 5.0V, T A e 25 § C.

Parameter

Conditions

Min

Typ Max

Units

Input Voltage Levels

V IH , Logic High

2.0

V IL , Logic Low

0.7

Input Currents

All Inputs Except MODE

V IL k V IN k V IH

b 1

m A

MODE

V IN e 0V

b 100

m A

Output Voltage Levels

V OH , Logic High

FS X and FS R Outputs, I OH e 3 mA

2.4

V OL , Logic Low

FS X and FS R Outputs, I OL e 5 mA

0.4

TS X Output, I OL e 5mA

0.4

Power Dissipation

BCLK e 2.048 MHz,

1.5

Operating Current

All Outputs Open-Circuit

Timing Specifications

Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC e 5.0V g 5%, T A e 0 § Cto a 70 § Cby

correlation with 100% electrical testing at T A e 25 § C. All other limits are assured by correlation with other production tests and/

or product design and characterization. Typicals specified at V CC e 5.0V, T A e 25 § C. All timing parameters are measured at

V OH e 2.0V and V OL e 0.7V.

See Definitions and Timing Conventions section for test methods information.

Symbol

Parameter

Conditions

Min

Max

Units

t PC

Period of Clock

BCLK, CLK C

480

t WCH

Width of Clock High

BCLK, CLK C

160

t WCL

Width of Clock Low

BCLK, CLK C

160

t SDC

Set-Up Time from D C to CLK C

t HCD

Hold Time from CLK C to D C

t SCC

Set-Up Time from CS to CLK C

t HCC

Hold Time from CLK C to CS

100

t SCHC

Set-Up Time from Channel Select to CLK C

t HCHC

Hold Time from Channel Select to CLK C

t DBF

Delay Time from BCLK Low to FS X/R 0±3

C L e 50 pF

100

High or Low

t HSYNC

Hold Time from BCLK to Frame Sync

t SSYNC

Set-Up Time from Frame Sync to BCLK

100

t DTL

Delay to TS X Low

C L e 50 pF

140

t DTH

Delay to TS X High

R L e 1k to V CC

140

t RC ,t FC

Rise and Fall Time of Clock

BCLK, CLK C

Block Diagram

TL/H/5118±2

Timing Diagrams

Control Interface

TL/H/5118±3

Output

TL/H/5118±4

Connection Diagrams

Dual-In-Line Package

Plastic Chip Carrier (PCC) Package

TL/H/5118±5

Order Number TP3155V

See NS Package Number V20A

TL/H/5118±6

Top View

Order Number TP3155N

See NS Package Number N20A

Pin Descriptions

Symbol

Description

Symbol Description

BCLK The bit clock input, which should run at the

same rate as that for the COMBO CODEC/

Filter COMBO.

XSYNC The transmit TS0 sync pulse input. Must be

synchronous with BCLK.

RSYNC/CH2 The function of this input is determined by the

MODE input (pin 9). In mode 1 this is the re-

ceive TS0 sync pulse, RSYNC, which must be

synchronous with BCLK. In mode 2 this is the

CH2 input for the MSB of the channel select

word.

FS X 1

A conventional CMOS frame sync output

which is normally low, and goes active-high

for 8 cycles of BCLK when a valid transmit

time slot assignment is made.

FS R 1

A conventional CMOS frame sync output

which is normally low, and goes active-high

for 8 cycles of BCLK when a valid receive

time slot assignment is made.

FS X 0

A transmit frame sync output similar to pin 1.

FS R 0

A receive frame sync output similar to pin 2.

TS X

An open-drain N-channel output which is nor-

mally high impedance but pulls low during any

active transmit time slot.

CH1

The input for the next significant bit of the

channel select word.

D C

The input for an 8-bit serial control word. X is

the first bit clocked in.

CH0

The input for the LSB of the channel select

word, which defines the frame sync output af-

fected by the following control word.

CL K C

The clock input for the control interface.

FS X 3

A transmit frame sync output similar to pin 1.

The active-low chip select for the control in-

terface.

FS R 3

A receive frame sync output similar to pin 2.

MODE

The mode select input. When left open-circuit

or connected to V CC , mode 1 is selected, and

when connected to GND, mode 2 is selected.

FS X 2

A transmit frame sync output similar to pin 1.

FS R 2

A receive frame sync output similar to pin 2.

V CC

The positive supply to the device. 5V g 5%.

GND

The 0V ground connection to the device.

Functional Description

OPERATING MODES

The TP3155 control interface requires an 8-bit serial control

word which is compatible wit h the T P3020/TP3021 and

2910/2911 CODECs. Two bits, X and R, define which of the

two groups of frame sync outputs, FS X 0toFS X 3orFS R 0to

FS R 3, is affected by the control word, and a 6-bit assign-

ment field specifies the selected time slot, from 0 to 31. A

frame sync output is active-high for one time slot, which is

always 8 cycles of BCLK. A frame may consist of any num-

ber of time slots up to 32. If a timeslot is assigned which is

beyond the number of time slots in a frame, the FS X or FS R

output to which it was assigned will remain inactive.

Two modes of operation are available. Mode 1 is for sys-

tems requiring different time slot assignments for the trans-

mit and receive direction of each channel. Mode 1 is select-

ed by leaving pin 9 (MODE) open-circuit or connecting it to

V CC . In this case, Pin 13 is the RSYNC input which defines

the start of each receive frame, and the four outputs,

FS R 0±FS R 3, are assigned with respect to RSYNC. The

XSYNC input defines the start of each transmit frame and

outputs FS X 0±FS X 3 are assigned with respect to XSYNC.

XSYNC may have any phase relationship with RSYNC. In-

puts CH0 and CH1 select the channel, from 0 to 3 (see

Table Ia).

Mode 2 provides the option of assigning all 8 frame sync

outputs with respect to the XSYNC input. Mode 2 is select-

ed by connecting pin 9 (MODE) to GND. This makes the

TP3155 TSAC useful for either an 8-channel undirectional

controller or for systems in which the transmit and receive

directions of each channel are always assigned to the same

time slot as the other, i.e., the FS X and FS R inputs on the

COMBO CODEC/Filter are hard-wired together. In this

case, logical selection of the channel to be assigned is

made via inputs CH0, CH1 and CH2 (see Table Ib).

POWER-UP INITIALIZATION

During power-up, all frame sync outputs, FS X 0±FS X 3 and

FS R 0±FS R 3, are inhibited and held low. No outputs will go

active until a valid time slot assignment is made.

LOADING CONTROL DATA

During the loading of control data, the binary code for the

selected channel must be set on inputs CH0 and CH1 (and

CH2 in mode 2), see Tables Ia and Ib.

Control data is cloc ked into the D C input on the falling

edges of CLK C while CS is low.

A new time slot assignment is transferred to the sele cted

assignment register on the high going transition of CS. The

new assignment is re-synchronized to the system clock

such that the new FS output pulses will start at t he next

complete valid time slot after the rising edge of CS.

TIME SLOT COUNTER OPERATION

At the start of TS0 of each transmit frame, defined by the

first falling edge of BCLK after XSYNC goes high, the trans-

mit time slot counter is reset to 000000 and begins to incre-

ment once every 8 cycles of BCLK. Each count is compared

with the 4 transmit assignment registers and, on finding a

match, a frame sync pulse is generated at that FS X output.

Similarly, the first falling edge of BCLK after RSYNC goes

high defines the start of receive TS0, and outputs

FS R 0±FS R 3 are generated with respect to TS0 when the

receive time slot counter matches the appropriate receive

assignment register.

TS X OUTPUT

In mode 1 (separate transmit and receive assignments), this

output pulls low whenever any FS X output pulse is being

generated. In mode 2, this output pulls low whenever any

FS X or FS R output is being gen erated. At all other times it is

open-circuit, allowing the TS X outputs of a number of

TSACS to be wire-ANDed together with a common pull-up

resistor. This signal can be used to control the TRI-STATE É

enable input of a line driver to buffer the transmit PCM bus

from the CODEC/Filters to the backplane.

TABLE Ia. Control Mode 1

(TP3020/TP3021 Compatible)

X R T5 T4 T3 T2 T1 T0

X is the first bit clocked into the D C input.

Control Data Format

T5 T4 T3 T2 T1 T0 Time Slot

0 0 0 0 0 0 0

0 0 0 0 0 1 1

0 0 0 0 1 0 2

0 1 1 1 1 0 30

0 1 1 1 1 1 31

1 X X X X X (Note 1)

CH1 CH0

Channel Selected

Assign to FS x 0 and/or FS R 0

Assign to FS x 1 and/or FS R 1

Assign to FS x 2 and/or FS R 2

Assign to FS x 3 and/or FS R 3

X R Action

0 0 Assign time slot to both selected FS X and FS R

0 1 Assign time slot to selected FS X only

1 0 Assign time slot to selected FS R only

1 1 Disable both selected FS X and FS R

TABLE Ib. Control Mode 2

CH2 CH1 CH0 Channel Selected

Assign to FS X 0

Assign to FS X 1

Assign to FS X 2

Assign to FS X 3

Assign to FS R 0

Assign to FS R 1

Assign to FS R 2

Assign to FS R 3

X R

Action

(

1 1 Disable selected output

Note 1: When T5 e 1, then the appropriate FS X or FS R output is inactive.

Assign time slot to selected output

1 0

0 0

0 1

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