KA3882C.pdf

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KA3882C/KA3883C SMPS Controller
www.fairchildsemi.com
KA3882C/KA3883C
SMPS Controller
Features
• Low Start Current 0.2mA (typ)
• Operating Range Up To 500KHz
• Cycle by Cycle Current Limiting
• Under Voltage Lock Out With Hysteresis
• Short Shutdown Delay Time: typ.100ns
• High Current Totem-pole Output
• Output Swing Limiting: 22V
Description
The KA3882C/KA3883C are fixed PWM controller for
Off-Line and DC to DC converter applications. The internal
circuits include UVLO, low start up current circuit,
temperature compensated reference, high gain error
amplifier, current sensing comparator, and high current
totem pole output for driving a POWER MOSFET. Also
KA3882C/KA3883C provide low start up current below
0.3mA and short shutdown delay time typ. 100ns. The
KA3882C has UVLO threshold of 16V(on) and 10V(off).
The KA3883C is 8.4V(on) and 7.6V(off). The KA3882C
and KA3883C can operate within 100% duty cycle.
8-DIP
8-SOP
1
1
Internal Block Diagram
7
V CC
29V
5V
V REF
SET/
RESET
V REF
8
5
GND
UVLO
Internal
Bias
Good LOGIC
1/2V REF
7
PWR
V C
Error Amp
C.S
Comp.
PWM
LATCH
+
-
1/3
V FB
2
R
22V
6
OUTPUT
1V
S
COMP
1
5
PWR
GND
C.S
3
T
R T /C T
4
OSCILLATOR
Rev. 1.0.0
©2001 Fairchild Semiconductor Corporation
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KA3882C/KA3883C
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Supply Voltage
V CC
30
V
Output Current
I O
± 1
A
Analog Inputs (pin 2, 3)
V I(ANA)
- 0.3 to 6.3
V
Error Amp. Output Sink Current
ISINK(EA)
10
mA
Power Dissipation
P D
1
W
Thermal Resistance, Junction-to-Air (Note4)
8-SOP
8-DIP
R
ja
280
95
C/W
Electrical Characteristics
(V CC = 15V, R T = 10K
, C T = 3.3nF, T A = 0
C to + 70
C ,Unless otherwise specified)
Parameter
Symbol
Conditions
Min. Typ. Max. Unit
REFERENCE SECTION
Output Voltage
V REF
T J = 25
C, I O = 1mA
4.9
5.0
5.1
V
Line Regulation
V REF
V CC = 12V to 25V
-
6
20
mV
Load Regulation
V REF
I O = 1mA to 20mA
-
6
25
mV
Output Short Circuit
ISC
Ta = 25
C
-
- 100 - 180 mA
OSILLATOR SECTION
Initial Accuracy
F OSC
T J = 25
C
47
52
57 KHz
Voltage Stability
ST V
V CC = 12V to 25V
-
0.2
1
%
Amplitude
VOSC
VPIN4, Peak to Peak
-
1.7
-
V
Discharge Current
I DISCHG T J = 25
C , Pin4 = 2V
7.8
8.3
8.8
mA
CURRENT SENSE SECTION
Gain
G V
(NOTE 2, 3)
2.85
3
3.15 V/V
Maximum Input Signal
VI(MAX) VPIN1 = 5V(NOTE 2)
0.9
1.0
1.1
V
PSRR
PSRR
V CC = 12V to 25V (NOTE 1, 2)
-
70
-
dB
Input Bias Current
I BIAS
-
-
- 2
-10
uA
Delay to Output
T D
V PIN3 = 0 V to 2V (NOTE1)
-
100 200
ns
2
214298845.012.png
KA3882C/KA3883C
Electrical Characteristics (Continued)
(V CC = 15V, R T = 10K
, C T = 3.3nF, T A = 0
C to + 70
C, Unless otherwise specified)
Parameter
Symbol
Conditions
Min. Typ. Max. Unit
ERROR AMPLIFIER SECTION
Input Voltage
V I
T PIN1 = 2.5V
2.42 2.50 2.58
V
Input Bias Current
I BIAS
-
-
-0.3
- 2
uA
Open Loop Gain
G VO
V O = 2V to 4V (NOTE 1)
65
90
-
dB
Unity Gain Bandwidth
GBW
T J = 25
C (NOTE 1)
0.7
1
-
MHz
PSRR
PSRR
V CC = 12V to 25V (NOTE 1)
60
70
-
dB
Output Sink Current
I SINK
V PIN2 = 2.7V
V PIN1 = 1.1V
2
6
-
A
Output Source Current
I SOURCE
V PIN2 = 2.3V
V PIN1 = 5.0V
-0.5
-0.8
-
mA
Output High Voltage
V OH
V PIN2 = 2.3V
R1 = 15K
to GND
5
6
-
V
Output Low Voltage
V OL
V PIN2 = 2.7V
R1 = 15K
to Pin8
-
0.8
1.1
V
OUTPUT SECTION
Output Low Level
V OL
I SINK = 20mA
-
0.1
0.4
V
I SINK = 200mA
-
1.5
2.2
V
Output High Level
V OH
I SOURCE = 20mA
13
13.5
-
V
I SOURCE = 200mA
12
13.5
-
V
Rise Time
t R
T J = 25
C , C1 = 1nF (NOTE 1)
-
40
100
ns
Fall Time
t F
T J = 25
C , C1 = 1nF (NOTE 1)
-
40
100
ns
Output Voltage Swing Limit
V OLIM
V CC = 27V, C1 = 1nF
-
22
-
V
UNDER VOLTAGE LOCKOUT SECTION
Start Threshold
V TH
KA3882C
15
16
17
V
KA3883C
7.8
8.4
9.0
V
Min. Operating Voltage
( After turn on )
KA3882C
9
10
11
V
V TL
KA3883C
7.0
7.6
8.2
V
PWM SECTION
Maximum Duty Cycle
D MAX
KA3882C/KA3883C
94
96
100
%
Minimum Duty Cycle
D MIN
-
-
-
0
%
TOTAL STANDBY CURRENT
Start-Up Current
I ST
-
-
0.2
0.4
A
Operating Supply Current
I CC
V PIN2 = V PIN3 = 0V
-
11
17
mA
V CC Zener Voltage
V Z
I CC = 25mA
-
29
-
V
V PIN3 (V PIN3 = 0 to 0.8V)
4. Junction-to-air thermal resistance test enviroments.
-. PCB information ;
Board thickness : 1.6mm , Board dimension : 76.2 X 114.3mm 2 , Ref. : EIA / JSED51-3 and EIA / JSED51-7
-. Board structure; Using the single layer PCB.
V PIN1
3
* Adjust V CC above the start threshold before setting at 15V
Notes :
1. These parameters, although guaranteed, are not 100% tested in production.
2. Parameter measured at trip point of latch with V2 = 0V.
3. Gain defined as: G V =
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KA3882C/KA3883C
Mechanical Dimensions
Package
8-DIP
6.40 ± 0.20
0.252 ±
0.008
#1
#8
#4
#5
5.08
0.200
3.30 ±
0.30
MAX
0.130 ±
0.012
7.62
0.300
3.40 ±
0.20
0.33
0.013
MIN
0.134 ±
0.008
–0.05
0.0 10 +0.00 4
–0.0 02
4
0.25 + 0.10
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KA3882C/KA3883C
Mechanical Dimensions (Continued)
Package
8-SOP
MIN
0.1~0.25
0.004~0.001
1.55 ± 0.20
0.061 ±
0.008
#1
#8
#4
#5
6.00 ±
0.30
1.80
0.071
0.236 ±
0.012
MAX
3.95 ± 0.20
0.156 ± 0.008
5.72
0.225
0.50 ±
0.20
0.020 ±
0.008
5
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