cd4093.pdf

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199623105 UNPDF
SEMICONDUCTOR TECHNICAL DATA
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L SUFFIX
CERAMIC
CASE 632
The MC14093B Schmitt trigger is constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic structure.
These devices find primary use where low power dissipation and/or high
noise immunity is desired. The MC14093B may be used in place of the
MC14011B quad 2–input NAND gate for enhanced noise immunity or to
“square up” slowly changing waveforms.
•
P SUFFIX
PLASTIC
CASE 646
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
D SUFFIX
SOIC
CASE 751A
•
Triple Diode Protection on All Inputs
•
Pin–for–Pin Compatible with CD4093
•
Can be Used to Replace MC14011B
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
T A = – 55 ° to 125 ° C for all packages.
•
Independent Schmitt–Trigger at each Input
MAXIMUM RATINGS* (Voltages Referenced to V SS )
ÎÎÎÎ
Symbol
Parameter
Value
Unit
V DD
DC Supply Voltage
– 0.5 to + 18.0
V
V in , V out
Input or Output Voltage (DC or Transient)
– 0.5 to V DD + 0.5
V
LOGIC DIAGRAM
I in , I out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
1
3
2
P D
Power Dissipation, per Package†
500
mW
T stg
Storage Temperature
– 65 to + 150
C
5
4
6
C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
T L
Lead Temperature (8–Second Soldering)
260
8
10
9
12
11
13
EQUIVALENT CIRCUIT SCHEMATIC
(1/4 OF CIRCUIT SHOWN)
V DD = PIN 14
V SS = PIN 7
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V in and
V out should be constrained to the range V SS
3
(V in or V out )
3
REV 3
1/94
W
MOTOROLA CMOS LOGIC DATA
MC14093B
1
V DD .
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V SS or V DD ). Unused outputs must be left open.
Motorola, Inc. 1995
199623105.017.png 199623105.018.png 199623105.019.png 199623105.020.png 199623105.001.png 199623105.002.png 199623105.003.png
ELECTRICAL CHARACTERISTICS (Voltages Refere nced to V SS )
ÎÎÎÎÎÎÎÎÎÎ
V DD
Vdc
– 55 C
25 C
125 C
V DD
Vdc
Characteristic
Symbol
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
“0” Level
V OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V in = V DD or 0
“1” Level
V OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
V in = 0 or V DD
Output Drive Current
(V OH = 2.5 Vdc)
I OH
mAdc
Source
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
(V OH = 4.6 Vdc)
(V OH = 9.5 Vdc)
(V OH = 13.5 Vdc)
(V OL = 0.4 Vdc)
Sink
I OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
(V OL = 0.5 Vdc)
(V OL = 1.5 Vdc)
Input Current
I in
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
m Adc
Input Capacitance
(V in = 0)
C in
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
I DD
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
m Adc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(C L = 50 pF on all outputs, all
buffers switching)
I T
5.0
10
15
I T = (1.2 m A/kHz) f + I DD
I T = (2.4
m Adc
m
A/kHz) f + I DD
I T = (3.6
m
A/kHz) f + I DD
Hysteresis Voltage
V H †
5.0
10
15
0.3
1.2
1.6
2.0
3.4
5.0
0.3
1.2
1.6
1.1
1.7
2.1
2.0
3.4
5.0
0.3
1.2
1.6
2.0
3.4
5.0
Vdc
Threshold Voltage
Positive–Going
Vdc
V T+
5.0
10
15
2.2
4.6
6.8
3.6
7.1
10.8
2.2
4.6
6.8
2.9
5.9
8.8
3.6
7.1
10.8
2.2
4.6
6.8
3.6
7.1
10.8
Negative–Going
V T–
5.0
10
15
0.9
2.5
4.0
2.8
5.2
7.4
0.9
2.5
4.0
1.9
3.9
5.8
2.8
5.2
7.4
0.9
2.5
4.0
2.8
5.2
7.4
Vdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25 C.
†To calculate total supply current at loads other than 50 pF:
I T (C L ) = I T (50 pF) + (C L – 50) Vfk
where: I T is in
m
A (per package), C L in pF, V = (V DD – V SS ) in volts, f in kHz is input frequency, and k = 0.004.
MC14093B
2
MOTOROLA CMOS LOGIC DATA
Characteristic
Symbol
Unit
199623105.004.png 199623105.005.png 199623105.006.png
SWITCHING CHARACTERISTICS (C L = 50 pF, T A = 25 C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic
Symbol
V DD
Vdc
Min
Typ #
Max
Unit
Output Rise Time
t TLH
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Output Fall Time
t THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
t PLH , t PHL
5.0
10
15
—
—
—
125
50
40
250
100
80
ns
#Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V DD
20 ns
20 ns
14
INPUT
90%
50%
10%
V DD
PULSE
GENERATOR
OUTPUT
V SS
V OH
t PHL
OUTPUT
t PLH
INPUT
7
V SS
C L
9 0%
5 0 10%
V OL
t THL
t TLH
Figure 1. Switching Time Test Circuit and Waveforms
V H
V DD
V H
V DD
V in
V in
V SS
V SS
V DD
V DD
V out
V out
V SS
V SS
(a) Schmitt Triggers will square up
(a) inputs with slow rise and fall times.
(b) A Schmitt trigger offers maximum
(b) noise immunity in gate applications.
Figure 2. Typical Schmitt Trigger Applications
MOTOROLA CMOS LOGIC DATA
MC14093B
3
199623105.007.png 199623105.008.png 199623105.009.png 199623105.010.png
14
I OH
14
I OL
V GS
V out
V out
All unused inputs
connected to ground.
7
7
All unused inputs
connected to ground.
V GS
0
c
b
a
10
a b c
15 Vdc
– 2.0
V GS = – 5.0 Vdc
8.0
a
b
V GS = 10 Vdc
a T A = – 55
°
C
C
b T A = + 125
°
– 4.0
6.0
c
°
C
a T A = – 55
C
c
C
c T A = + 125
°
– 6.0
4.0
°
C
– 10 Vdc
b
c
b
– 15 Vdc
a
– 8.0
2.0
b
5.0 Vdc
a
c
a
– 10
0
– 10
– 8.0
– 6.0
– 4.0
– 2.0
0
0
2.0
4.0
6.0
8.0
10
V DS , DRAIN VOLTAGE (Vdc)
V DS , DRAIN VOLTAGE (Vdc)
Figure 3. Typical Output Source
Characteristics Test Circuit
Figure 4. Typical Output Sink
Characteristics Test Circuit
V DD
PIN ASSIGNMENT
IN 1 A
1
14
V DD
IN 2 A
2
13
IN 2 D
OUT A
3
12
IN 1 D
OUT B
4
11
OUT D
IN 1 B
5
10
OUT C
IN 2 B
6
9
IN 2 C
V SS
7
8
IN 1C
0 0
V T–
V T+
V DD
V H
V in , INPUT VOLTAGE (Vdc)
Figure 5. Typical Transfer Characteristics
MC14093B
4
MOTOROLA CMOS LOGIC DATA
b T A = + 25
°
b T A = + 25
199623105.011.png 199623105.012.png
OUTLINE DIMENSIONS
–A–
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
14
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
1
7
C
L
INCHES
MILLIMETERS
DIM MIN
MAX
MIN
MAX
A
0.750 0.785 19.05 19.94
B
0.245 0.280
6.23
7.11
–T–
SEATING
PLANE
C
0.155 0.200
3.94
5.08
K
D
0.015 0.020
0.39
0.50
F
0.055 0.065
1.40
1.65
G
0.100 BSC
2.54 BSC
F
G
N
M
J
0.008 0.015
0.21
0.38
K
0.125 0.170
3.18
4.31
D
14 PL
J
14 PL
L
0.300 BSC
7.62 BSC
0.25 (0.010)
M
T
A
S
0.25 (0.010)
T
B
M
0
15
0
1.01
M
S
N
0.020 0.040
0.51
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
14
8
B
1
7
A
INCHES
MILLIMETERS
DIM MIN
MAX
MIN
MAX
A
0.715 0.770 18.16 19.56
F
L
B
0.240 0.260
6.10
6.60
C
0.145 0.185
3.69
4.69
D
0.015 0.021
0.38
0.53
C
F
0.040 0.070
1.02
1.78
G
0.100 BSC
2.54 BSC
H
0.052 0.095
1.32
2.41
J
J
0.008 0.015
0.20
0.38
N
K
0.115 0.135
2.92
3.43
SEATING
PLANE
K
L
0.300 BSC
7.62 BSC
M
0
10
0
10
H
G
D
M
N
0.015 0.039
0.39
1.01
MOTOROLA CMOS LOGIC DATA
MC14093B
5
15
199623105.013.png 199623105.014.png 199623105.015.png 199623105.016.png

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